Merge pull request #476 from awaisabbas-rs/yosys_only_flow

Yosys only support added in OpenFPGA

.github/workflows/build.yml

@@ -229,6 +229,7 @@ jobs:
       fail-fast: false
       matrix:
         config:
+          - name: basic_reg_yosys_only_test
           - name: basic_reg_test
           - name: fpga_verilog_reg_test
           - name: fpga_bitstream_reg_test
@@ -282,6 +283,7 @@ jobs:
       fail-fast: false
       matrix:
         config:
+          - name: basic_reg_yosys_only_test
           - name: basic_reg_test
           - name: fpga_verilog_reg_test
           - name: fpga_bitstream_reg_test

docs/source/manual/openfpga_flow/run_fpga_task.rst

@@ -94,7 +94,7 @@ Declaring all the above sections are mandatory.
 General Section
 ^^^^^^^^^^^^^^^
 
-.. option:: fpga_flow=<yosys_vpr|vpr_blif>
+.. option:: fpga_flow=<yosys_vpr|vpr_blif|yosys>
 
     This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.
 

openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh

@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+source openfpga.sh
+PYTHON_EXEC=python3.8
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "Basic regression tests for Yosys-only flow";
+
+echo -e "Testing configuration chain of a K4N4 FPGA";
+run-task basic_tests/yosys_only --debug --show_thread_logs
+
+# Repgression test to test multi-user enviroment
+cp -r */*/basic_tests/yosys_only /tmp/
+cd /tmp/ && run-task yosys_only --debug --show_thread_logs

openfpga_flow/scripts/run_fpga_flow.py

@@ -273,23 +273,32 @@ def main():
 
     if (args.fpga_flow == "vpr_blif"):
         collect_files_for_vpr()
-    logger.info("Running OpenFPGA Shell Engine ")
-    run_openfpga_shell()
-    if args.end_flow_with_test:
-        run_netlists_verification()
+    if (args.fpga_flow == "yosys"):
+        run_yosys_with_abc()
+    if not (args.fpga_flow == "yosys"):
+        logger.info("Running OpenFPGA Shell Engine ")
+        run_openfpga_shell()
+        if args.end_flow_with_test:
+            run_netlists_verification()
 
     ExecTime["End"] = time.time()
     def timestr(x): return humanize.naturaldelta(timedelta(seconds=x)) \
         if "humanize" in sys.modules else str(int(x)) + " Sec "
-    TimeInfo = ("Openfpga_flow completed, " +
-                "Total Time Taken %s " %
-                timestr(ExecTime["End"]-ExecTime["Start"]) +
-                "VPR Time %s " %
-                timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"]))
-    TimeInfo += ("Verification Time %s " %
-                 timestr(ExecTime["VerificationEnd"] -
-                         ExecTime["VerificationStart"])
-                 if args.end_flow_with_test else "")
+    
+    if (args.fpga_flow == "yosys"):
+        TimeInfo = ("Openfpga_flow completed, " +
+                    "Total Time Taken %s " %
+                    timestr(ExecTime["End"]-ExecTime["Start"]))
+    else:
+        TimeInfo = ("Openfpga_flow completed, " +
+                    "Total Time Taken %s " %
+                    timestr(ExecTime["End"]-ExecTime["Start"]) +
+                    "VPR Time %s " %
+                    timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"]))
+        TimeInfo += ("Verification Time %s " %
+                     timestr(ExecTime["VerificationEnd"] -
+                             ExecTime["VerificationStart"])
+                     if args.end_flow_with_test else "")
     logger.info(TimeInfo)
     exit()
 

openfpga_flow/scripts/run_fpga_task.py

@@ -96,13 +96,14 @@ def main():
     for eachtask in args.tasks:
         logger.info("Currently running task %s" % eachtask)
         eachtask = eachtask.replace("\\", "/").split("/")
-        job_run_list = generate_each_task_actions(eachtask)
+        job_run_list, GeneralSection = generate_each_task_actions(eachtask)
         if args.remove_run_dir:
             continue
         eachtask = "_".join(eachtask)
         if not args.test_run:
             run_actions(job_run_list)
-            collect_results(job_run_list)
+            if not (GeneralSection.get("fpga_flow") == "yosys"):
+                collect_results(job_run_list)
         else:
             pprint.pprint(job_run_list)
     logger.info("Task execution completed")
@@ -350,7 +351,7 @@ def generate_each_task_actions(taskname):
     logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' %
                 (len(archfile_list), len(benchmark_list), len(ScriptSections)))
     logger.info('Created total %d jobs' % len(flow_run_cmd_list))
-    return flow_run_cmd_list
+    return flow_run_cmd_list,GeneralSection
 
 # Make the directory name unique by including the benchmark index in the list.
 # This is because benchmarks may share the same top module names

openfpga_flow/tasks/basic_tests/yosys_only/config/task.conf

@@ -0,0 +1,44 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=
+openfpga_fast_configuration=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_chan_width = 300
+
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+#end_flow_with_test=