From fc52a4696cd6e2e69e74c448fe5377e97393e3b0 Mon Sep 17 00:00:00 2001 From: Awais Abbas Date: Thu, 6 Jan 2022 14:44:11 +0500 Subject: [PATCH 1/6] Yosys only support added in OpenFPGA --- openfpga_flow/scripts/run_fpga_flow.py | 35 ++++++++++++++++---------- openfpga_flow/scripts/run_fpga_task.py | 7 +++--- 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 08e33b0c7..23754aacf 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -273,23 +273,32 @@ def main(): if (args.fpga_flow == "vpr_blif"): collect_files_for_vpr() - logger.info("Running OpenFPGA Shell Engine ") - run_openfpga_shell() - if args.end_flow_with_test: - run_netlists_verification() + if (args.fpga_flow == "yosys"): + run_yosys_with_abc() + if not (args.fpga_flow == "yosys"): + logger.info("Running OpenFPGA Shell Engine ") + run_openfpga_shell() + if args.end_flow_with_test: + run_netlists_verification() ExecTime["End"] = time.time() def timestr(x): return humanize.naturaldelta(timedelta(seconds=x)) \ if "humanize" in sys.modules else str(int(x)) + " Sec " - TimeInfo = ("Openfpga_flow completed, " + - "Total Time Taken %s " % - timestr(ExecTime["End"]-ExecTime["Start"]) + - "VPR Time %s " % - timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"])) - TimeInfo += ("Verification Time %s " % - timestr(ExecTime["VerificationEnd"] - - ExecTime["VerificationStart"]) - if args.end_flow_with_test else "") + + if (args.fpga_flow == "yosys"): + TimeInfo = ("Openfpga_flow completed, " + + "Total Time Taken %s " % + timestr(ExecTime["End"]-ExecTime["Start"])) + else: + TimeInfo = ("Openfpga_flow completed, " + + "Total Time Taken %s " % + timestr(ExecTime["End"]-ExecTime["Start"]) + + "VPR Time %s " % + timestr(ExecTime["VPREnd"]-ExecTime["VPRStart"])) + TimeInfo += ("Verification Time %s " % + timestr(ExecTime["VerificationEnd"] - + ExecTime["VerificationStart"]) + if args.end_flow_with_test else "") logger.info(TimeInfo) exit() diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index b257526bb..e7f7688d3 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -96,13 +96,14 @@ def main(): for eachtask in args.tasks: logger.info("Currently running task %s" % eachtask) eachtask = eachtask.replace("\\", "/").split("/") - job_run_list = generate_each_task_actions(eachtask) + job_run_list, GeneralSection = generate_each_task_actions(eachtask) if args.remove_run_dir: continue eachtask = "_".join(eachtask) if not args.test_run: run_actions(job_run_list) - collect_results(job_run_list) + if not (GeneralSection.get("fpga_flow") == "yosys"): + collect_results(job_run_list) else: pprint.pprint(job_run_list) logger.info("Task execution completed") @@ -350,7 +351,7 @@ def generate_each_task_actions(taskname): logger.info('Found %d Architectures %d Benchmarks & %d Script Parameters' % (len(archfile_list), len(benchmark_list), len(ScriptSections))) logger.info('Created total %d jobs' % len(flow_run_cmd_list)) - return flow_run_cmd_list + return flow_run_cmd_list,GeneralSection # Make the directory name unique by including the benchmark index in the list. # This is because benchmarks may share the same top module names From 598c5e6b75a768ea1c043c9b0d29b12152b033bf Mon Sep 17 00:00:00 2001 From: Awais Abbas Date: Fri, 14 Jan 2022 15:37:47 +0500 Subject: [PATCH 2/6] Test case for yosys-only flow added --- .../basic_tests/yosys_only/config/task.conf | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/yosys_only/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/yosys_only/config/task.conf b/openfpga_flow/tasks/basic_tests/yosys_only/config/task.conf new file mode 100644 index 000000000..074873d1d --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/yosys_only/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +#end_flow_with_test= From 793e40cb95a042a697cb5b7e09cf0c4fd8023e9a Mon Sep 17 00:00:00 2001 From: Awais Abbas Date: Fri, 14 Jan 2022 15:39:26 +0500 Subject: [PATCH 3/6] basic_reg test for yosys-only flow added in OpenFPGA regression test scripts --- .../basic_reg_yosys_only_test.sh | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100755 openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh diff --git a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh new file mode 100755 index 000000000..174204249 --- /dev/null +++ b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "Basic regression tests for Yosys-only flow"; + +echo -e "Testing configuration chain of a K4N4 FPGA"; +run-task basic_tests/verific_test --debug --show_thread_logs + +# Repgression test to test multi-user enviroment +cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/ +cd /tmp/ && run-task configuration_chain --debug --show_thread_logs From 469b3a960cc38826a0e5975419ae28412690ffa8 Mon Sep 17 00:00:00 2001 From: Awais Abbas Date: Fri, 14 Jan 2022 15:44:26 +0500 Subject: [PATCH 4/6] basic reg test updated --- .../regression_test_scripts/basic_reg_yosys_only_test.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh index 174204249..372ceb8f4 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_yosys_only_test.sh @@ -9,8 +9,8 @@ PYTHON_EXEC=python3.8 echo -e "Basic regression tests for Yosys-only flow"; echo -e "Testing configuration chain of a K4N4 FPGA"; -run-task basic_tests/verific_test --debug --show_thread_logs +run-task basic_tests/yosys_only --debug --show_thread_logs # Repgression test to test multi-user enviroment -cp -r */*/basic_tests/full_testbench/configuration_chain /tmp/ -cd /tmp/ && run-task configuration_chain --debug --show_thread_logs +cp -r */*/basic_tests/yosys_only /tmp/ +cd /tmp/ && run-task yosys_only --debug --show_thread_logs From ad7d29b975d88b4bc886a4eab0aefb9edd2e64c2 Mon Sep 17 00:00:00 2001 From: Awais Abbas Date: Fri, 14 Jan 2022 15:45:22 +0500 Subject: [PATCH 5/6] build.yml flow is updated with basic_reg_yosys_only_test --- .github/workflows/build.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 04977e863..2b2d65cba 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -229,6 +229,7 @@ jobs: fail-fast: false matrix: config: + - name: basic_reg_yosys_only_test - name: basic_reg_test - name: fpga_verilog_reg_test - name: fpga_bitstream_reg_test @@ -282,6 +283,7 @@ jobs: fail-fast: false matrix: config: + - name: basic_reg_yosys_only_test - name: basic_reg_test - name: fpga_verilog_reg_test - name: fpga_bitstream_reg_test From 54d4f30592d9ff3c7323c5ccab538f0ce6b3d4e6 Mon Sep 17 00:00:00 2001 From: Awais Abbas Date: Fri, 14 Jan 2022 16:14:48 +0500 Subject: [PATCH 6/6] OpenFPGA Documentation updated for yosys only support --- docs/source/manual/openfpga_flow/run_fpga_task.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/openfpga_flow/run_fpga_task.rst b/docs/source/manual/openfpga_flow/run_fpga_task.rst index afb2ccdbd..b4f87a73a 100644 --- a/docs/source/manual/openfpga_flow/run_fpga_task.rst +++ b/docs/source/manual/openfpga_flow/run_fpga_task.rst @@ -94,7 +94,7 @@ Declaring all the above sections are mandatory. General Section ^^^^^^^^^^^^^^^ -.. option:: fpga_flow= +.. option:: fpga_flow= This option defines which OpenFPGA flow to run. By default ``yosys_vpr`` is executed.