refactored fpga_define.v generation
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@ -264,8 +264,14 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
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init_pb_types_num_iopads();
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init_pb_types_num_iopads();
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/* init_grids_num_mode_bits(); */
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/* init_grids_num_mode_bits(); */
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/* TODO: This is the old function, which will be deprecated when refactoring is done */
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/*
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dump_verilog_defines_preproc(src_dir_path,
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dump_verilog_defines_preproc(src_dir_path,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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*/
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print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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dump_verilog_simulation_preproc(src_dir_path,
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dump_verilog_simulation_preproc(src_dir_path,
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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@ -12,6 +12,7 @@
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_naming.h"
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#include "verilog_global.h"
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#include "verilog_writer_utils.h"
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#include "verilog_writer_utils.h"
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#include "verilog_auxiliary_netlists.h"
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#include "verilog_auxiliary_netlists.h"
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@ -104,3 +105,51 @@ void print_include_netlists(const std::string& src_dir,
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/* Close the file stream */
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/* Close the file stream */
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fp.close();
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fp.close();
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}
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}
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/********************************************************************
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* Print a Verilog file containing preprocessing flags
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* which are used enable/disable some features in FPGA Verilog modules
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*******************************************************************/
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void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
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const t_syn_verilog_opts& fpga_verilog_opts) {
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std::string verilog_fname = src_dir + std::string(defines_verilog_file_name);
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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/* Validate the file stream */
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check_file_handler(fp);
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/* Print the title */
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print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules"));
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/* To enable timing */
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if (TRUE == fpga_verilog_opts.include_timing) {
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print_verilog_define_flag(fp, std::string(verilog_timing_preproc_flag), 1);
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fp << std::endl;
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}
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/* To enable timing */
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if (TRUE == fpga_verilog_opts.include_signal_init) {
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print_verilog_define_flag(fp, std::string(verilog_signal_init_preproc_flag), 1);
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fp << std::endl;
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}
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/* To enable formal verfication flag */
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if (TRUE == fpga_verilog_opts.print_formal_verification_top_netlist) {
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print_verilog_define_flag(fp, std::string(verilog_formal_verification_preproc_flag), 1);
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fp << std::endl;
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}
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/* To enable functional verfication with Icarus */
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if (TRUE == fpga_verilog_opts.include_icarus_simulator) {
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print_verilog_define_flag(fp, std::string(icarus_simulator_flag), 1);
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fp << std::endl;
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}
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/* Close the file stream */
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fp.close();
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}
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@ -3,10 +3,14 @@
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#include <string>
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#include <string>
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#include "circuit_library.h"
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#include "circuit_library.h"
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#include "vpr_types.h"
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void print_include_netlists(const std::string& src_dir,
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void print_include_netlists(const std::string& src_dir,
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const std::string& circuit_name,
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const std::string& circuit_name,
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const std::string& reference_benchmark_file,
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const std::string& reference_benchmark_file,
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const CircuitLibrary& circuit_lib);
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const CircuitLibrary& circuit_lib);
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void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
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const t_syn_verilog_opts& fpga_verilog_opts);
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#endif
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#endif
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@ -55,6 +55,17 @@ void print_verilog_include_netlist(std::fstream& fp,
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fp << "`include \"" << netlist_name << "\"" << std::endl;
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fp << "`include \"" << netlist_name << "\"" << std::endl;
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}
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}
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/********************************************************************
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* Print Verilog codes to define a preprocessing flag
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*******************************************************************/
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void print_verilog_define_flag(std::fstream& fp,
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const std::string& flag_name,
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const int& flag_value) {
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check_file_handler(fp);
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fp << "`define " << flag_name << " " << flag_value << std::endl;
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}
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/************************************************
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/************************************************
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* Generate include files for a Verilog netlist
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* Generate include files for a Verilog netlist
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***********************************************/
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***********************************************/
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@ -26,6 +26,10 @@ void print_verilog_file_header(std::fstream& fp,
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void print_verilog_include_netlist(std::fstream& fp,
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void print_verilog_include_netlist(std::fstream& fp,
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const std::string& netlist_name);
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const std::string& netlist_name);
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void print_verilog_define_flag(std::fstream& fp,
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const std::string& flag_name,
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const int& flag_value);
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void print_verilog_include_defines_preproc_file(std::fstream& fp,
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void print_verilog_include_defines_preproc_file(std::fstream& fp,
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const std::string& verilog_dir);
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const std::string& verilog_dir);
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