Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
This commit is contained in:
tangxifan
commit
115411941b
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@ -3,6 +3,6 @@ FROM ubuntu:16.04
|
|||
RUN apt-get update -qq -y
|
||||
RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev
|
||||
|
||||
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
|
||||
RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default
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||||
|
||||
|
||||
|
|
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|||
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@ -3,13 +3,13 @@
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|||
|
||||
# Set variables
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||||
my_pwd=$PWD
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||||
fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
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||||
vpr_path=${my_pwd}/vpr7_x2p/vpr
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||||
benchmark="pipelined_8b_adder"
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||||
fpga_flow_scripts="${my_pwd}/fpga_flow/scripts"
|
||||
vpr_path="${my_pwd}/vpr7_x2p/vpr"
|
||||
benchmark="test_modes"
|
||||
include_netlists="_include_netlists.v"
|
||||
compiled_file="compiled_$benchmark"
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||||
tb_formal_postfix="_top_formal_verification_random_tb"
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||||
verilog_output_dirname="${vpr_path}${benchmark}_Verilog"
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||||
verilog_dirname="${vpr_path}/${benchmark}_Verilog"
|
||||
log_file="${benchmark}_sim.log"
|
||||
new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh"
|
||||
template_sh="${PWD}/ERI_demo/eri_demo.sh"
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||||
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@ -28,7 +28,8 @@ cd $my_pwd
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|||
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||||
# Start the script -> run the fpga generation -> run the simulation -> check the log file
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||||
source $new_reg_sh # Leave us in vpr folder
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||||
iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
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||||
cd $my_pwd
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||||
iverilog -o $compiled_file ${verilog_dirname}/SRC/${benchmark}${include_netlists} -s ${benchmark}${tb_formal_postfix}
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||||
vvp $compiled_file -j 64 >> $log_file
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||||
|
||||
result=`grep "Succeed" $log_file`
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||||
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|
@ -36,14 +37,13 @@ if ["$result" = ""]; then
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|||
result=`grep "Failed" $log_file`
|
||||
if ["$result" = ""]; then
|
||||
echo "Unexpected error, Verification didn't run"
|
||||
cd $my_pwd
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||||
exit 1
|
||||
else
|
||||
echo "Verification failed"
|
||||
cd $my_pwd
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||||
exit 2
|
||||
fi
|
||||
else
|
||||
echo "Verification succeed"
|
||||
cd $my_pwd
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||||
gtkwave ${benchmark}_formal.vcd &
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||||
fi
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||||
|
||||
|
|
|
|||
|
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@ -3,18 +3,18 @@
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|||
|
||||
# Set variables
|
||||
# For FPGA-Verilog ONLY
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||||
benchmark="pipelined_8b_adder"
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||||
benchmark="test_modes"
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||||
OpenFPGA_path="OPENFPGAPATHKEYWORD"
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||||
verilog_output_dirname="${benchmark}_Verilog"
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||||
verilog_output_dirpath="$vpr_path"
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||||
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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||||
# VPR critical inputs
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||||
template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml"
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arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml"
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||||
blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif"
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||||
act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act "
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||||
verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v"
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||||
vpr_route_chan_width="300"
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||||
template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml"
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||||
arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml"
|
||||
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
|
||||
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
|
||||
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
|
||||
vpr_route_chan_width="200"
|
||||
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
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||||
ff_path="$vpr_path/VerilogNetlists/ff.v"
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||||
new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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||||
|
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@ -23,15 +23,13 @@ ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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|||
arch_ff_keyword="FFPATHKEYWORD"
|
||||
tb_formal_ext="_formal_random_top_tb.v"
|
||||
formal_postfix="_top_formal_verification"
|
||||
clk_unmapped="clk\[0:0\]"
|
||||
clk_mapped="clk_fm"
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||||
|
||||
# Remove previous designs
|
||||
rm -rf $verilog_output_dirpath/$verilog_output_dirname
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||||
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||||
mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
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||||
|
||||
#cd $fpga_flow_scripts
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||||
cd $fpga_flow_scripts
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||||
perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
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||||
perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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||||
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||||
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@ -39,14 +37,10 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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|||
cd $vpr_path
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||||
|
||||
# Run VPR
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||||
./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp
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||||
./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping --nodisp
|
||||
|
||||
cd $fpga_flow_scripts
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||||
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
|
||||
|
||||
rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
|
||||
perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
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||||
cd -
|
||||
|
||||
sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v
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||||
|
||||
|
|
|
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|
|
@ -1,42 +0,0 @@
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|||
#!/bin/bash
|
||||
# Example of how to run vpr
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||||
|
||||
# Set variables
|
||||
# For FPGA-Verilog ONLY
|
||||
benchmark="pipelined_32b_adder"
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||||
OpenFPGA_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA"
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||||
verilog_output_dirname="${benchmark}_Verilog"
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||||
verilog_output_dirpath="$vpr_path"
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||||
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"
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||||
# VPR critical inputs
|
||||
template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml"
|
||||
arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml"
|
||||
blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif"
|
||||
act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act "
|
||||
verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v"
|
||||
vpr_route_chan_width="300"
|
||||
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
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||||
ff_path="$vpr_path/VerilogNetlists/ff.v"
|
||||
new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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||||
ff_keyword="GENERATED_DIR_KEYWORD"
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||||
ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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||||
arch_ff_keyword="FFPATHKEYWORD"
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||||
|
||||
# Remove previous designs
|
||||
#rm -rf $verilog_output_dirpath/$verilog_output_dirname
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||||
|
||||
mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
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||||
|
||||
cd $fpga_flow_scripts
|
||||
perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
|
||||
perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
|
||||
|
||||
# Move to vpr folder
|
||||
cd $vpr_path
|
||||
|
||||
# Run VPR
|
||||
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
|
||||
|
||||
cd $fpga_flow_scripts
|
||||
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
|
||||
cd -
|
||||
|
|
@ -1,95 +0,0 @@
|
|||
clk 0.5 0.2
|
||||
wen 0.5 0.2
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||||
wen_st0 0.5 0.2
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||||
wen_st1 0.5 0.2
|
||||
ren 0.5 0.2
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||||
raddr[0] 0.5 0.2
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||||
raddr[1] 0.5 0.2
|
||||
raddr[2] 0.5 0.2
|
||||
raddr[3] 0.5 0.2
|
||||
raddr[4] 0.5 0.2
|
||||
raddr[5] 0.5 0.2
|
||||
waddr[0] 0.5 0.2
|
||||
waddr[1] 0.5 0.2
|
||||
waddr[2] 0.5 0.2
|
||||
waddr[3] 0.5 0.2
|
||||
waddr[4] 0.5 0.2
|
||||
waddr[5] 0.5 0.2
|
||||
waddr_st0[0] 0.5 0.2
|
||||
waddr_st0[1] 0.5 0.2
|
||||
waddr_st0[2] 0.5 0.2
|
||||
waddr_st0[3] 0.5 0.2
|
||||
waddr_st0[4] 0.5 0.2
|
||||
waddr_st0[5] 0.5 0.2
|
||||
waddr_st1[0] 0.5 0.2
|
||||
waddr_st1[1] 0.5 0.2
|
||||
waddr_st1[2] 0.5 0.2
|
||||
waddr_st1[3] 0.5 0.2
|
||||
waddr_st1[4] 0.5 0.2
|
||||
waddr_st1[5] 0.5 0.2
|
||||
a[0] 0.5 0.2
|
||||
a[1] 0.5 0.2
|
||||
a[2] 0.5 0.2
|
||||
a[3] 0.5 0.2
|
||||
a[4] 0.5 0.2
|
||||
a[5] 0.5 0.2
|
||||
a[6] 0.5 0.2
|
||||
a_st0[0] 0.5 0.2
|
||||
a_st0[1] 0.5 0.2
|
||||
a_st0[2] 0.5 0.2
|
||||
a_st0[3] 0.5 0.2
|
||||
a_st0[4] 0.5 0.2
|
||||
a_st0[5] 0.5 0.2
|
||||
a_st0[6] 0.5 0.2
|
||||
a_st1[0] 0.5 0.2
|
||||
a_st1[1] 0.5 0.2
|
||||
a_st1[2] 0.5 0.2
|
||||
a_st1[3] 0.5 0.2
|
||||
a_st1[4] 0.5 0.2
|
||||
a_st1[5] 0.5 0.2
|
||||
a_st1[6] 0.5 0.2
|
||||
b[0] 0.5 0.2
|
||||
b[1] 0.5 0.2
|
||||
b[2] 0.5 0.2
|
||||
b[3] 0.5 0.2
|
||||
b[4] 0.5 0.2
|
||||
b[5] 0.5 0.2
|
||||
b[6] 0.5 0.2
|
||||
b_st0[0] 0.5 0.2
|
||||
b_st0[1] 0.5 0.2
|
||||
b_st0[2] 0.5 0.2
|
||||
b_st0[3] 0.5 0.2
|
||||
b_st0[4] 0.5 0.2
|
||||
b_st0[5] 0.5 0.2
|
||||
b_st0[6] 0.5 0.2
|
||||
b_st1[0] 0.5 0.2
|
||||
b_st1[1] 0.5 0.2
|
||||
b_st1[2] 0.5 0.2
|
||||
b_st1[3] 0.5 0.2
|
||||
b_st1[4] 0.5 0.2
|
||||
b_st1[5] 0.5 0.2
|
||||
b_st1[6] 0.5 0.2
|
||||
q[0] 0.5 0.2
|
||||
q[1] 0.5 0.2
|
||||
q[2] 0.5 0.2
|
||||
q[3] 0.5 0.2
|
||||
q[4] 0.5 0.2
|
||||
q[5] 0.5 0.2
|
||||
q[6] 0.5 0.2
|
||||
q[7] 0.5 0.2
|
||||
AplusB[0] 0.5 0.2
|
||||
AplusB[1] 0.5 0.2
|
||||
AplusB[2] 0.5 0.2
|
||||
AplusB[3] 0.5 0.2
|
||||
AplusB[4] 0.5 0.2
|
||||
AplusB[5] 0.5 0.2
|
||||
AplusB[6] 0.5 0.2
|
||||
AplusB[7] 0.5 0.2
|
||||
cint01 0.5 0.2
|
||||
cint02 0.5 0.2
|
||||
cint03 0.5 0.2
|
||||
cint04 0.5 0.2
|
||||
cint05 0.5 0.2
|
||||
cint06 0.5 0.2
|
||||
cint07 0.5 0.2
|
||||
zero00 0 0
|
||||
|
|
@ -1,137 +0,0 @@
|
|||
# Benchmark pipelined_32b_adder
|
||||
.model pipelined_32b_adder
|
||||
.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6]
|
||||
.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7]
|
||||
|
||||
# Start pipeline
|
||||
# Pipeline a
|
||||
.subckt shift D=a[0] clk=clk Q=a_st0[0]
|
||||
.subckt shift D=a_st0[0] clk=clk Q=a_st1[0]
|
||||
.subckt shift D=a[1] clk=clk Q=a_st0[1]
|
||||
.subckt shift D=a_st0[1] clk=clk Q=a_st1[1]
|
||||
.subckt shift D=a[2] clk=clk Q=a_st0[2]
|
||||
.subckt shift D=a_st0[2] clk=clk Q=a_st1[2]
|
||||
.subckt shift D=a[3] clk=clk Q=a_st0[3]
|
||||
.subckt shift D=a_st0[3] clk=clk Q=a_st1[3]
|
||||
.subckt shift D=a[4] clk=clk Q=a_st0[4]
|
||||
.subckt shift D=a_st0[4] clk=clk Q=a_st1[4]
|
||||
.subckt shift D=a[5] clk=clk Q=a_st0[5]
|
||||
.subckt shift D=a_st0[5] clk=clk Q=a_st1[5]
|
||||
.subckt shift D=a[6] clk=clk Q=a_st0[6]
|
||||
.subckt shift D=a_st0[6] clk=clk Q=a_st1[6]
|
||||
|
||||
# Pipeline b
|
||||
.subckt shift D=b[0] clk=clk Q=b_st0[0]
|
||||
.subckt shift D=b_st0[0] clk=clk Q=b_st1[0]
|
||||
.subckt shift D=b[1] clk=clk Q=b_st0[1]
|
||||
.subckt shift D=b_st0[1] clk=clk Q=b_st1[1]
|
||||
.subckt shift D=b[2] clk=clk Q=b_st0[2]
|
||||
.subckt shift D=b_st0[2] clk=clk Q=b_st1[2]
|
||||
.subckt shift D=b[3] clk=clk Q=b_st0[3]
|
||||
.subckt shift D=b_st0[3] clk=clk Q=b_st1[3]
|
||||
.subckt shift D=b[4] clk=clk Q=b_st0[4]
|
||||
.subckt shift D=b_st0[4] clk=clk Q=b_st1[4]
|
||||
.subckt shift D=b[5] clk=clk Q=b_st0[5]
|
||||
.subckt shift D=b_st0[5] clk=clk Q=b_st1[5]
|
||||
.subckt shift D=b[6] clk=clk Q=b_st0[6]
|
||||
.subckt shift D=b_st0[6] clk=clk Q=b_st1[6]
|
||||
|
||||
# Pipeline waddr
|
||||
.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0]
|
||||
.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0]
|
||||
.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1]
|
||||
.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1]
|
||||
.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2]
|
||||
.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2]
|
||||
.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3]
|
||||
.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3]
|
||||
.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4]
|
||||
.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4]
|
||||
.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5]
|
||||
.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5]
|
||||
# Pipeline wen
|
||||
.subckt shift D=wen clk=clk Q=wen_st0
|
||||
.subckt shift D=wen_st0 clk=clk Q=wen_st1
|
||||
# End pipeline
|
||||
|
||||
# Start adder
|
||||
.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0]
|
||||
.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1]
|
||||
.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2]
|
||||
.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3]
|
||||
.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4]
|
||||
.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5]
|
||||
.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6]
|
||||
.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7]
|
||||
# End adder
|
||||
|
||||
# Start DPRAM
|
||||
.subckt dpram clk=clk wen=wen_st1 ren=ren \
|
||||
waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \
|
||||
waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \
|
||||
raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \
|
||||
raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \
|
||||
d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \
|
||||
d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
|
||||
d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
|
||||
d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
|
||||
d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
|
||||
d_in[30]=zero00 d_in[31]=zero00 \
|
||||
d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \
|
||||
d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \
|
||||
d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
|
||||
d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
|
||||
d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
|
||||
d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
|
||||
d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \
|
||||
d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn
|
||||
# End DPRAM
|
||||
|
||||
# Start global variable
|
||||
.names zero00
|
||||
0
|
||||
# End global variable
|
||||
|
||||
|
||||
.end
|
||||
|
||||
# Start blackbox definition
|
||||
.model dpram
|
||||
.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
|
||||
waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \
|
||||
raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
|
||||
d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
|
||||
d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
|
||||
d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
|
||||
d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \
|
||||
d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \
|
||||
d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \
|
||||
d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \
|
||||
d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63]
|
||||
.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
|
||||
d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
|
||||
d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
|
||||
d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
|
||||
d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \
|
||||
d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \
|
||||
d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \
|
||||
d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \
|
||||
d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \
|
||||
d_out[63]
|
||||
.blackbox
|
||||
.end
|
||||
|
||||
|
||||
.model adder
|
||||
.inputs a b cin
|
||||
.outputs cout sumout
|
||||
.blackbox
|
||||
.end
|
||||
|
||||
|
||||
.model shift
|
||||
.inputs D clk
|
||||
.outputs Q
|
||||
.blackbox
|
||||
.end
|
||||
# End blackbox definition
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/////////////////////////////////////
|
||||
// //
|
||||
// ERI summit demo-benchmark //
|
||||
// pipelined_8b_adder.v //
|
||||
// by Aurelien //
|
||||
// //
|
||||
/////////////////////////////////////
|
||||
|
||||
`timescale 1 ns/ 1 ps
|
||||
|
||||
module pipelined_8b_adder(
|
||||
clk,
|
||||
raddr,
|
||||
waddr,
|
||||
ren,
|
||||
wen,
|
||||
a,
|
||||
b,
|
||||
q );
|
||||
|
||||
input clk;
|
||||
input[5:0] raddr;
|
||||
input[5:0] waddr;
|
||||
input ren;
|
||||
input wen;
|
||||
input[6:0] a;
|
||||
input[6:0] b;
|
||||
output[7:0] q;
|
||||
|
||||
reg[63:0] ram[7:0];
|
||||
reg[6:0] a_st0;
|
||||
reg[6:0] a_st1;
|
||||
reg[6:0] b_st0;
|
||||
reg[6:0] b_st1;
|
||||
reg[8:0] waddr_st0;
|
||||
reg[8:0] waddr_st1;
|
||||
reg wen_st0;
|
||||
reg wen_st1;
|
||||
reg[7:0] q_int;
|
||||
|
||||
wire[7:0] AplusB;
|
||||
|
||||
assign AplusB = a_st1 + b_st1;
|
||||
assign q = q_int;
|
||||
|
||||
always@(posedge clk) begin
|
||||
waddr_st0 <= waddr;
|
||||
waddr_st1 <= waddr_st0;
|
||||
a_st0 <= a;
|
||||
a_st1 <= a_st0;
|
||||
b_st0 <= b;
|
||||
b_st1 <= b_st0;
|
||||
wen_st0 <= wen;
|
||||
wen_st1 <= wen_st0;
|
||||
if(wen_st1) begin
|
||||
ram[waddr_st1] <= AplusB;
|
||||
end
|
||||
if(ren) begin
|
||||
q_int <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,219 +0,0 @@
|
|||
`timescale 1 ns/ 100 ps
|
||||
|
||||
`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v"
|
||||
|
||||
module pipelined_8b_adder_top_formal_verification_random_tb();
|
||||
reg clk;
|
||||
reg[5:0] raddr;
|
||||
reg[5:0] waddr;
|
||||
reg ren;
|
||||
reg wen;
|
||||
reg[6:0] a;
|
||||
reg[6:0] b;
|
||||
wire[7:0] q_gfpga;
|
||||
wire[7:0] q_bench;
|
||||
reg[7:0] q_flag;
|
||||
|
||||
pipelined_8b_adder_top_formal_verification DUT(
|
||||
.clk_fm (clk),
|
||||
.raddr_0__fm (raddr[0]),
|
||||
.raddr_1__fm (raddr[1]),
|
||||
.raddr_2__fm (raddr[2]),
|
||||
.raddr_3__fm (raddr[3]),
|
||||
.raddr_4__fm (raddr[4]),
|
||||
.raddr_5__fm (raddr[5]),
|
||||
.waddr_0__fm (waddr[0]),
|
||||
.waddr_1__fm (waddr[1]),
|
||||
.waddr_2__fm (waddr[2]),
|
||||
.waddr_3__fm (waddr[3]),
|
||||
.waddr_4__fm (waddr[4]),
|
||||
.waddr_5__fm (waddr[5]),
|
||||
.ren_fm (ren),
|
||||
.wen_fm (wen),
|
||||
.a_0__fm (a[0]),
|
||||
.a_1__fm (a[1]),
|
||||
.a_2__fm (a[2]),
|
||||
.a_3__fm (a[3]),
|
||||
.a_4__fm (a[4]),
|
||||
.a_5__fm (a[5]),
|
||||
.a_6__fm (a[6]),
|
||||
.b_0__fm (b[0]),
|
||||
.b_1__fm (b[1]),
|
||||
.b_2__fm (b[2]),
|
||||
.b_3__fm (b[3]),
|
||||
.b_4__fm (b[4]),
|
||||
.b_5__fm (b[5]),
|
||||
.b_6__fm (b[6]),
|
||||
.out_q_0__fm (q_gfpga[0]),
|
||||
.out_q_1__fm (q_gfpga[1]),
|
||||
.out_q_2__fm (q_gfpga[2]),
|
||||
.out_q_3__fm (q_gfpga[3]),
|
||||
.out_q_4__fm (q_gfpga[4]),
|
||||
.out_q_5__fm (q_gfpga[5]),
|
||||
.out_q_6__fm (q_gfpga[6]),
|
||||
.out_q_7__fm (q_gfpga[7])
|
||||
);
|
||||
|
||||
pipelined_8b_adder ref0(
|
||||
.clk (clk),
|
||||
.raddr (raddr),
|
||||
.waddr (waddr),
|
||||
.ren (ren),
|
||||
.wen (wen),
|
||||
.a (a),
|
||||
.b (b),
|
||||
.q (q_bench)
|
||||
);
|
||||
|
||||
integer nb_error = 0;
|
||||
integer count = 0;
|
||||
integer lim_max = 64 - 1;
|
||||
integer write_complete = 0;
|
||||
|
||||
//----- Initialization
|
||||
initial begin
|
||||
clk <= 1'b0;
|
||||
a <= 7'h00;
|
||||
b <= 7'h00;
|
||||
wen <= 1'b0;
|
||||
ren <= 1'b0;
|
||||
waddr <= 9'h000;
|
||||
raddr <= 9'h000;
|
||||
while(1) begin
|
||||
#2.5
|
||||
clk <= !clk;
|
||||
end
|
||||
end
|
||||
|
||||
//----- Input Stimulis
|
||||
always@(negedge clk) begin
|
||||
if(write_complete == 0) begin
|
||||
wen <= 1'b1;
|
||||
ren <= 1'b0;
|
||||
count <= count + 1;
|
||||
waddr <= waddr + 1;
|
||||
if(count == lim_max) begin
|
||||
write_complete = 1;
|
||||
end
|
||||
end else begin
|
||||
wen <= $random;
|
||||
ren <= $random;
|
||||
waddr <= $random;
|
||||
raddr <= $random;
|
||||
end
|
||||
a <= $random;
|
||||
b <= $random;
|
||||
end
|
||||
|
||||
|
||||
always@(negedge clk) begin
|
||||
if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin
|
||||
q_flag[0] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[0] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin
|
||||
q_flag[1] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[1] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin
|
||||
q_flag[2] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[2] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin
|
||||
q_flag[3] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[3] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin
|
||||
q_flag[4] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[4] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin
|
||||
q_flag[5] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[5] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin
|
||||
q_flag[6] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[6] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin
|
||||
q_flag[7] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[7] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge q_flag[0]) begin
|
||||
if(q_flag[0]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[0] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[1]) begin
|
||||
if(q_flag[1]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[1] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[2]) begin
|
||||
if(q_flag[2]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[2] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[3]) begin
|
||||
if(q_flag[3]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[3] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[4]) begin
|
||||
if(q_flag[4]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[4] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[5]) begin
|
||||
if(q_flag[5]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[5] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[6]) begin
|
||||
if(q_flag[6]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[6] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[7]) begin
|
||||
if(q_flag[7]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[7] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpfile("pipelined_8b_adder_formal.vcd");
|
||||
$dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
#1500 // Can be changed by the user for his need
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
$display("Simulation Failed with %d error(s)", nb_error);
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
31
README.md
31
README.md
|
|
@ -5,25 +5,23 @@
|
|||
|
||||
## Introduction
|
||||
|
||||
OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
|
||||
The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification testbenches/scripts. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.<br />
|
||||
|
||||
## Compilation
|
||||
|
||||
The different ways of compiling can be found in the **./compilation** folder.<br />
|
||||
Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md).
|
||||
The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/compilation) folder.<br />
|
||||
Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
|
||||
|
||||
**Compilation steps:**
|
||||
1. Clone the repository (git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA)
|
||||
2. Create a folder named build in OpenPFGA repository (mkdir build && cd build)
|
||||
3. Create Makefile in this folder using cmake (cmake .. -DCMAKE_BUILD_TYPE=debug)
|
||||
4. Compile the tool and its dependencies (make)
|
||||
|
||||
*We currently implemented OpenFPGA for:*
|
||||
|
||||
*1. Ubuntu 18.04*
|
||||
*2. Red Hat 7.5*
|
||||
*3. MacOS High Sierra 10.13.4*
|
||||
1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it*
|
||||
2. mkdir build && cd build # *Create a folder named build in OpenPFGA repository*
|
||||
3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create Makefile in this folder using cmake*
|
||||
4. make # *Compile the tool and its dependencies*
|
||||
|
||||
*We currently implemented OpenFPGA for:*<br />
|
||||
*1. Ubuntu 16.04*<br />
|
||||
*2. Red Hat 7.5*<br />
|
||||
*3. MacOS Mojiva 10.13.4*<br /><br />
|
||||
*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.*
|
||||
|
||||
## Documentation
|
||||
|
|
@ -31,9 +29,8 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl
|
|||
|
||||
## Tutorial
|
||||
|
||||
You can find in the folder **./tutorials**. This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them.
|
||||
|
||||
Through this tutorial users can learn how to use the flow and set the dependancies.
|
||||
|
||||
You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them.
|
||||
|
||||
Through this tutorial users can learn how to use the flow and set the dependancies.<br />
|
||||
The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through trainings and explain folder oraganization as well as referencing tips and used keywords.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,14 @@
|
|||
Command-line Options for FPGA Bitstream Generator
|
||||
=================================================
|
||||
|
||||
**Under Construction**
|
||||
All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
|
||||
|
||||
FPGA-Verilog Supported Option::
|
||||
|
||||
--fpga_bitstream_generator
|
||||
|
||||
.. csv-table:: Commmand-line Option of FPGA-Bitstream
|
||||
:header: "Command Options", "Description"
|
||||
:widths: 15, 30
|
||||
|
||||
"--fpga_bitstream_generator", "Turn on the FPGA-Bitstream and output a .bitstream file containing FPGA configuration."
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@ FPGA-Verilog Supported Options::
|
|||
:widths: 15, 30
|
||||
|
||||
"--fpga_verilog", "Turn on the FPGA-Verilog."
|
||||
<<<<<<< HEAD
|
||||
"--fpga_verilog_dir <dir_path>", "Specify the directory that all the Verilog files will be outputted to <dir_path> is the destination directory."
|
||||
"--fpga_verilog_include_timing", "Includes the timings found in the XML file."
|
||||
"--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
|
||||
|
|
@ -30,7 +29,6 @@ FPGA-Verilog Supported Options::
|
|||
"--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck."
|
||||
"--fpga_verilog_print_top_auto_testbench \
|
||||
<path_to_the_verilog_benchmark>", "Prints the testbench associated with the given benchmark. Determines the type of autodeck."
|
||||
=======
|
||||
"--fpga_verilog_dir <dir_path>", "Specify the directory where all the Verilog files will be outputted to. <dir_path> is the destination directory."
|
||||
"--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file."
|
||||
"--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case"
|
||||
|
|
@ -46,8 +44,6 @@ FPGA-Verilog Supported Options::
|
|||
"--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR"
|
||||
"--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool"
|
||||
"--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping"
|
||||
"", ""
|
||||
>>>>>>> f56adc681567b73c7826228641e089482dffc009
|
||||
|
||||
.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are:
|
||||
|
||||
|
|
|
|||
|
|
@ -187,8 +187,8 @@
|
|||
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
|
||||
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
|
||||
</transistors>
|
||||
<module_spice_models>
|
||||
<spice_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
|
||||
<module_circuit_models>
|
||||
<circuit_model type="inv_buf" name="INV1X" prefix="INV1X" is_default="1">
|
||||
<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
|
|
@ -198,9 +198,9 @@
|
|||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="4"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
|
|
@ -209,9 +209,9 @@
|
|||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="3" f_per_stage="4"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="INV4X" prefix="INV4X" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
|
|
@ -220,9 +220,9 @@
|
|||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="3" f_per_stage="4"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="INV2X" prefix="INV2X" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
|
|
@ -231,9 +231,9 @@
|
|||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="inv_buf" name="buf2" prefix="buf2" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_buf_level="2" f_per_stage="2"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf2" prefix="buf2" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="2"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<delay_matrix type="rise" in_port="in" out_port="out">
|
||||
|
|
@ -242,8 +242,8 @@
|
|||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="inv_buf" name="buf1" prefix="buf1" is_default="0" >
|
||||
</circuit_model>
|
||||
<circuit_model type="inv_buf" name="buf1" prefix="buf1" is_default="0" >
|
||||
<design_technology type="cmos" topology="buffer" size="1" tapered="off"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
|
|
@ -253,8 +253,8 @@
|
|||
<delay_matrix type="fall" in_port="in" out_port="out">
|
||||
10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
|
||||
</circuit_model>
|
||||
<circuit_model type="pass_gate" name="TGATEX1" prefix="TGATEX1" is_default="1">
|
||||
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
|
||||
<input_buffer exist="off"/>
|
||||
<output_buffer exist="off"/>
|
||||
|
|
@ -268,8 +268,8 @@
|
|||
<delay_matrix type="fall" in_port="in sel selb" out_port="out">
|
||||
10e-12 5e-12 5e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="gate" name="OR2" prefix="OR2" is_default="1">
|
||||
</circuit_model>
|
||||
<circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
|
||||
<design_technology type="cmos" topology="OR"/>
|
||||
<input_buffer exist="off"/>
|
||||
<output_buffer exist="off"/>
|
||||
|
|
@ -282,141 +282,141 @@
|
|||
<delay_matrix type="fall" in_port="a b" out_port="out">
|
||||
10e-12 10e-12
|
||||
</delay_matrix>
|
||||
</spice_model>
|
||||
<spice_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
|
||||
</circuit_model>
|
||||
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="off"/>
|
||||
<output_buffer exist="off"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
|
||||
</spice_model>
|
||||
<spice_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
|
||||
</circuit_model>
|
||||
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="off"/>
|
||||
<output_buffer exist="off"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
|
||||
</spice_model>
|
||||
<spice_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<!--mux2to1 subckt_name="mux2to1"/-->
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
</spice_model>
|
||||
<spice_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV4X"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV4X"/>
|
||||
<!--mux2to1 subckt_name="mux2to1"/-->
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
</spice_model>
|
||||
<spice_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="true">
|
||||
</circuit_model>
|
||||
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV4X"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV4X"/>
|
||||
<!--mux2to1 subckt_name="mux2to1"/-->
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="sram" prefix="sram" size="1"/>
|
||||
<port type="output" prefix="out" size="1"/>
|
||||
</spice_model>
|
||||
</circuit_model>
|
||||
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
|
||||
<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
|
||||
<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
|
||||
<port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
|
||||
</spice_model>
|
||||
<spice_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<lut_input_buffer exist="on" spice_model_name="buf2"/>
|
||||
<lut_intermediate_buffer exist="on" spice_model_name="buf1" location_map="-1-1-"/>
|
||||
<lut_input_inverter exist="on" spice_model_name="INV2X"/>
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="6" tri_state_map="----11" spice_model_name="OR2"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
|
||||
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-1-"/>
|
||||
<lut_input_inverter exist="on" circuit_model_name="INV2X"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
|
||||
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="64"/>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
|
||||
</spice_model>
|
||||
<spice_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||
</circuit_model>
|
||||
<circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
|
||||
<design_technology type="cmos" fracturable_lut="true"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<lut_input_inverter exist="on" spice_model_name="INV1X"/>
|
||||
<lut_intermediate_buffer exist="on" spice_model_name="buf1" location_map="-1-"/>
|
||||
<lut_input_buffer exist="on" spice_model_name="buf2"/>
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="--11" spice_model_name="OR2"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<lut_input_inverter exist="on" circuit_model_name="INV1X"/>
|
||||
<lut_intermediate_buffer exist="on" circuit_model_name="buf1" location_map="-1-"/>
|
||||
<lut_input_buffer exist="on" circuit_model_name="buf2"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="4" tri_state_map="--11" circuit_model_name="OR2"/>
|
||||
<port type="output" prefix="lut2_out" size="4" lut_frac_level="2" lut_output_mask="0,1,2,3"/>
|
||||
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
|
||||
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
|
||||
<port type="sram" prefix="sram" size="16"/>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
|
||||
</spice_model>
|
||||
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||
</circuit_model>
|
||||
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
|
||||
<spice_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
|
||||
<circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="FFPATHKEYWORD">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
|
||||
<!-- <port type="input" prefix="pSet" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/> -->
|
||||
<port type="input" prefix="D" size="1"/>
|
||||
<port type="output" prefix="Q" size="1"/>
|
||||
<port type="output" prefix="Qb" size="1"/>
|
||||
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
|
||||
</spice_model>
|
||||
<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
|
||||
</circuit_model>
|
||||
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="inout" prefix="pad" size="1"/>
|
||||
<port type="sram" prefix="en" size="1" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
|
||||
<!--port type="sram" prefix="enb" size="1" mode_select="true" spice_model_name="sc_dff_compact" default_val="0"/-->
|
||||
<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
|
||||
<!--port type="sram" prefix="enb" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="0"/-->
|
||||
<port type="input" prefix="outpad" size="1"/>
|
||||
<!-- <port type="input" prefix="zin" size="1" is_global="true" default_val="0" /> -->
|
||||
<port type="output" prefix="inpad" size="1"/>
|
||||
</spice_model>
|
||||
</circuit_model>
|
||||
<!-- Hard logic definition for heterogenous blocks -->
|
||||
<spice_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
|
||||
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<port type="input" prefix="a" size="1"/>
|
||||
<port type="input" prefix="b" size="1"/>
|
||||
<port type="input" prefix="cin" size="1"/>
|
||||
<port type="output" prefix="sumout" size="1"/>
|
||||
<port type="output" prefix="cout" size="1"/>
|
||||
</spice_model>
|
||||
<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
|
||||
</circuit_model>
|
||||
<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v">
|
||||
<design_technology type="cmos"/>
|
||||
<input_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<output_buffer exist="on" spice_model_name="INV1X"/>
|
||||
<pass_gate_logic spice_model_name="TGATEX1"/>
|
||||
<input_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<output_buffer exist="on" circuit_model_name="INV1X"/>
|
||||
<pass_gate_logic circuit_model_name="TGATEX1"/>
|
||||
<port type="input" prefix="in" size="1"/>
|
||||
<port type="output" prefix="out" size="2"/>
|
||||
</spice_model>
|
||||
</circuit_model>
|
||||
|
||||
</module_spice_models>
|
||||
</module_circuit_models>
|
||||
</spice_settings>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
|
|
@ -443,9 +443,9 @@
|
|||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<sram area="6">
|
||||
<verilog organization="scan-chain" spice_model_name="sc_dff_compact"/>
|
||||
<!--verilog organization="memory-bank" spice_model_name="sram6T_blwl"/-->
|
||||
<spice organization="standalone" spice_model_name="sram6T" />
|
||||
<verilog organization="scan-chain" circuit_model_name="sc_dff_compact"/>
|
||||
<!--verilog organization="memory-bank" circuit_model_name="sram6T_blwl"/-->
|
||||
<spice organization="standalone" circuit_model_name="sram6T" />
|
||||
</sram>
|
||||
<chan_width_distr>
|
||||
<io width="1.000000"/>
|
||||
|
|
@ -456,7 +456,7 @@
|
|||
</device>
|
||||
|
||||
<cblocks>
|
||||
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
||||
<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
||||
</switch>
|
||||
</cblocks>
|
||||
<switchlist>
|
||||
|
|
@ -473,25 +473,25 @@
|
|||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
||||
<switch type="mux" name="sb_mux_L16" R="0" Cin="0" Cout="" Tdel="1.3e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
||||
</switch>
|
||||
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" spice_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
||||
<switch type="mux" name="sb_mux_L4" R="0" Cin="0" Cout="" Tdel="0.72e-9" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
|
||||
</switch>
|
||||
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
|
||||
<switch type="mux" name="sb_mux_L2" R="115" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
|
||||
</switch>
|
||||
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" spice_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
|
||||
<switch type="mux" name="sb_mux_L1" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
|
||||
</switch>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
|
||||
<segment freq="0.13" length="16" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
|
||||
<mux name="sb_mux_L16"/>
|
||||
<sb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1</cb>
|
||||
</segment>
|
||||
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" spice_model_name="chan_segment">
|
||||
<segment freq="0.87" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
|
||||
<mux name="sb_mux_L4"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
|
|
@ -515,7 +515,7 @@
|
|||
|
||||
<!-- physical design description -->
|
||||
<mode name="io_phy" disabled_in_packing="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" spice_model_name="iopad" mode_bits="1">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad" mode_bits="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
|
|
@ -616,7 +616,7 @@
|
|||
<clock name="clk" num_pins="1"/>
|
||||
|
||||
<mode name="fle_phy" disabled_in_packing="true">
|
||||
<!--pb_type name="fle_phy" num_pb="1" spice_model_name="fle_phy">
|
||||
<!--pb_type name="fle_phy" num_pb="1" circuit_model_name="fle_phy">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="2"/>
|
||||
|
|
@ -628,13 +628,13 @@
|
|||
<input name="regchain" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<pb_type name="frac_lut6" blif_model=".frac_lut6" mode_bits="11" num_pb="1" spice_model_name="frac_lut6">
|
||||
<pb_type name="frac_lut6" blif_model=".frac_lut6" mode_bits="11" num_pb="1" circuit_model_name="frac_lut6">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="lut4_out" num_pins="4"/>
|
||||
<output name="lut5_out" num_pins="2"/>
|
||||
<output name="lut6_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2" spice_model_name="adder">
|
||||
<pb_type name="adder_phy" blif_model=".subckt adder" num_pb="2" circuit_model_name="adder">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
|
|
@ -656,7 +656,7 @@
|
|||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" spice_model_name="static_dff">
|
||||
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" circuit_model_name="static_dff">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
|
|
@ -951,31 +951,31 @@
|
|||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]" spice_model_name="mux_2level">
|
||||
<complete name="crossbar0" input="clb.I2 clb.I3 fle[9:0].out" output="fle[9:0].in[0]" circuit_model_name="mux_2level">
|
||||
<delay_constant max="90.2e-12" in_port="clb.I2 clb.I3" out_port="fle[9:0].in[0]" />
|
||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[0]" />
|
||||
</complete>
|
||||
<complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]" spice_model_name="mux_2level">
|
||||
<complete name="crossbar1" input="clb.I1 clb.I2 fle[9:0].out" output="fle[9:0].in[1]" circuit_model_name="mux_2level">
|
||||
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I2" out_port="fle[9:0].in[1]" />
|
||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[1]" />
|
||||
</complete>
|
||||
<complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]" spice_model_name="mux_2level">
|
||||
<complete name="crossbar2" input="clb.I0 clb.I1 fle[9:0].out" output="fle[9:0].in[2]" circuit_model_name="mux_2level">
|
||||
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I1" out_port="fle[9:0].in[2]" />
|
||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[2]" />
|
||||
</complete>
|
||||
<complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]" spice_model_name="mux_2level">
|
||||
<complete name="crossbar3" input="clb.I1 clb.I3 fle[9:0].out" output="fle[9:0].in[3]" circuit_model_name="mux_2level">
|
||||
<delay_constant max="90.2e-12" in_port="clb.I1 clb.I3" out_port="fle[9:0].in[3]" />
|
||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[3]" />
|
||||
</complete>
|
||||
<complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]" spice_model_name="mux_2level">
|
||||
<complete name="crossbar4" input="clb.I0 clb.I2 fle[9:0].out" output="fle[9:0].in[4]" circuit_model_name="mux_2level">
|
||||
<delay_constant max="90.2e-12" in_port="clb.I0 clb.I2" out_port="fle[9:0].in[4]" />
|
||||
<delay_constant max="70.2e-12" in_port="fle[9:0].out" out_port="fle[9:0].in[4]" />
|
||||
</complete>
|
||||
<complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]" spice_model_name="mux_2level">
|
||||
<complete name="crossbar5" input="clb.I0 clb.I3 fle[9:0].out" output="fle[9:0].in[5]" circuit_model_name="mux_2level">
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||
</complete>
|
||||
<complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin" spice_model_name="mux_2level">
|
||||
<complete name="carry_in" input="clb.cin clb.cin_trick fle[9:0].out" output="fle[0:0].cin" circuit_model_name="mux_2level">
|
||||
<!-- Put all inter-block carry chain delay on this one edge -->
|
||||
<delay_constant max="0.16e-9" in_port="clb.cin clb.cin_trick" out_port="fle[0:0].cin"/>
|
||||
<!--pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/-->
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1358,9 +1358,6 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
|
|||
if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) {
|
||||
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}";
|
||||
}
|
||||
if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
|
||||
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
|
||||
}
|
||||
if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
|
||||
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
|
||||
}
|
||||
|
|
@ -1446,6 +1443,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
|
|||
if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) {
|
||||
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping";
|
||||
}
|
||||
if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
|
||||
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
|
||||
}
|
||||
}
|
||||
|
||||
# FPGA Bitstream Generator Options
|
||||
|
|
|
|||
|
|
@ -16,6 +16,9 @@ ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v"
|
|||
dir_keyword="GENERATED_DIR_KEYWORD"
|
||||
|
||||
rm -rf ${pwd_path}/results_OpenPithon
|
||||
|
||||
cd ${pwd_path}/arch
|
||||
mkdir -p generated # create folder to save rewritten architecture
|
||||
cd ${pwd_path}/scripts
|
||||
|
||||
# Replace keyword in config and architecture files
|
||||
|
|
|
|||
|
|
@ -40,7 +40,11 @@ OpenFPGA requires all the dependancies listed below:
|
|||
|
||||
## Docker
|
||||
|
||||
If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands:
|
||||
If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command:
|
||||
- docker run lnis/open_fpga:release <br />
|
||||
*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".*
|
||||
|
||||
Or a container where you can build OpenFPGA yourself can be created with the following commands:
|
||||
- docker build . -t open_fpga
|
||||
- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash<br />
|
||||
[*docker download link*](https://www.docker.com/products/docker-desktop)
|
||||
|
|
|
|||
|
|
@ -17,10 +17,10 @@ In this folder are saved the architecture files. These files are Hardware descri
|
|||
This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders:
|
||||
- **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module
|
||||
- **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module.
|
||||
- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#benchmark-list)
|
||||
- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#benchmark-list)
|
||||
|
||||
## configs
|
||||
This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#configuration-file)
|
||||
This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#configuration-file)
|
||||
|
||||
## scripts
|
||||
This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.<br />
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# FPGA flow
|
||||
|
||||
This tutorial will help the user to understand how to use OpenFPGA flow.<br />
|
||||
During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/folder_organization.md).
|
||||
During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md).
|
||||
|
||||
## Running fpga_flow.pl
|
||||
|
||||
|
|
@ -16,13 +16,13 @@ cd fpga_flow<br />
|
|||
|
||||
By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.<br />
|
||||
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.<br />
|
||||
The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md).<br />
|
||||
The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).<br />
|
||||
There is 3 important things to see:
|
||||
- All FPGA-Verilog options have been activated
|
||||
- fpga_flow.pl calls a configuration file through "config_file" variable
|
||||
- fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable
|
||||
|
||||
## Configuration file
|
||||
### Configuration file
|
||||
|
||||
In this file paths have to be full path. Relative path could lead to errors.<br />
|
||||
The file is organized in 3 parts:
|
||||
|
|
@ -64,7 +64,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St
|
|||
|
||||
*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
|
||||
|
||||
## Benchmark list
|
||||
### Benchmark list
|
||||
|
||||
The benchmark folder contains 3 sub-folders:
|
||||
* **Blif**: contains .blif and .act of benchmarks
|
||||
|
|
@ -76,3 +76,21 @@ The benchmark list file can contain as many benchmarks as available in the same
|
|||
top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
|
||||
|
||||
*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
|
||||
|
||||
|
||||
## Modifying flow
|
||||
Once dependancies are understood, we can modify the flow by changing the architecture and the route channel width.
|
||||
|
||||
### Experiment
|
||||
|
||||
* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial
|
||||
* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
|
||||
* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List
|
||||
* replace "200" with "300" in tuto_benchmark.txt
|
||||
* cd OPENFPGAPATHKEYWORD/fpga_flow
|
||||
* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
|
||||
* ./tuto_fpga_flow.sh
|
||||
|
||||
### Explanation
|
||||
|
||||
With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed.
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -3,8 +3,8 @@
|
|||
OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.<br />
|
||||
Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.<br /><br />
|
||||
These tutorials are organized as follow:
|
||||
* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md)
|
||||
* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md)
|
||||
* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
|
||||
* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
|
||||
* Architecture modification
|
||||
|
||||
## Folder organization
|
||||
|
|
|
|||
|
|
@ -1052,9 +1052,9 @@ static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,
|
|||
* We should have a spice_model_name if this mode defines the transistor-level circuit design
|
||||
* Since this is a leaf node
|
||||
*/
|
||||
pb_type->spice_model_name = my_strdup(FindProperty(Parent, "spice_model_name", FALSE));
|
||||
pb_type->spice_model_name = my_strdup(FindProperty(Parent, "circuit_model_name", FALSE));
|
||||
pb_type->spice_model = NULL;
|
||||
ezxml_set_attr(Parent, "spice_model_name", NULL);
|
||||
ezxml_set_attr(Parent, "circuit_model_name", NULL);
|
||||
/* Multi-mode CLB support:
|
||||
* We can read the mode configuration bits if they are defined
|
||||
*/
|
||||
|
|
@ -1400,7 +1400,7 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
|
|||
|
||||
|
||||
/* Xifan TANG: SPICE Support */
|
||||
Prop = FindProperty(Cur, "spice_model_name", FALSE);
|
||||
Prop = FindProperty(Cur, "circuit_model_name", FALSE);
|
||||
/* Default spice_model will be define later*/
|
||||
mode->interconnect[i].spice_model_name = my_strdup(Prop);
|
||||
mode->interconnect[i].spice_model = NULL;
|
||||
|
|
@ -1408,7 +1408,7 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
|
|||
mode->interconnect[i].fan_in = 0;
|
||||
mode->interconnect[i].fan_out = 0;
|
||||
mode->interconnect[i].num_mux = 0;
|
||||
ezxml_set_attr(Cur, "spice_model_name", NULL);
|
||||
ezxml_set_attr(Cur, "circuit_model_name", NULL);
|
||||
/* Get sram offset */
|
||||
mode->interconnect[i].spice_model_sram_offset = GetIntProperty(Cur, "spice_model_sram_offset", FALSE, 0);
|
||||
ezxml_set_attr(Cur, "spice_model_sram_offset", NULL);
|
||||
|
|
@ -3250,9 +3250,9 @@ static void ProcessSegments(INOUTP ezxml_t Parent,
|
|||
(*Segs)[i].Rmetal = GetFloatProperty(Node, "Rmetal", timing_enabled, 0);
|
||||
(*Segs)[i].Cmetal = GetFloatProperty(Node, "Cmetal", timing_enabled, 0);
|
||||
/* Xifan TANG: SPICE Model Support*/
|
||||
(*Segs)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE));
|
||||
(*Segs)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE));
|
||||
(*Segs)[i].spice_model = NULL;
|
||||
ezxml_set_attr(Node, "spice_model_name", NULL);
|
||||
ezxml_set_attr(Node, "circuit_model_name", NULL);
|
||||
/* Get Power info */
|
||||
/*
|
||||
(*Segs)[i].Cmetal_per_m = GetFloatProperty(Node, "Cmetal_per_m", FALSE,
|
||||
|
|
@ -3528,9 +3528,9 @@ static void ProcessSwitches(INOUTP ezxml_t Parent,
|
|||
FALSE, 1);
|
||||
|
||||
/* Xifan TANG: Spice Model Support */
|
||||
(*Switches)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE));
|
||||
(*Switches)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE));
|
||||
(*Switches)[i].spice_model = NULL;
|
||||
ezxml_set_attr(Node, "spice_model_name", NULL);
|
||||
ezxml_set_attr(Node, "circuit_model_name", NULL);
|
||||
/* Xifan TANG : Read in MUX structure*/
|
||||
/* Default, we use tree */
|
||||
structure_type = FindProperty(Node, "structure", FALSE);
|
||||
|
|
@ -3643,9 +3643,9 @@ static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,
|
|||
/* Spice Model Support: Xifan TANG
|
||||
* We should have a spice_model_name for this direct connection
|
||||
*/
|
||||
(*Directs)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE));
|
||||
(*Directs)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE));
|
||||
(*Directs)[i].spice_model = NULL;
|
||||
ezxml_set_attr(Node,"spice_model_name",NULL);
|
||||
ezxml_set_attr(Node,"circuit_model_name",NULL);
|
||||
|
||||
|
||||
(*Directs)[i].line = Node->line;
|
||||
|
|
|
|||
|
|
@ -451,8 +451,8 @@ static void ProcessSpiceModelBuffer(ezxml_t Node,
|
|||
read_spice_model = FALSE;
|
||||
}
|
||||
|
||||
buffer->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", read_spice_model));
|
||||
ezxml_set_attr(Node, "spice_model_name", NULL);
|
||||
buffer->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", read_spice_model));
|
||||
ezxml_set_attr(Node, "circuit_model_name", NULL);
|
||||
|
||||
/*Find Type*/
|
||||
Prop = my_strdup(FindProperty(Node, "topology", read_buf_info));
|
||||
|
|
@ -475,9 +475,9 @@ static void ProcessSpiceModelBuffer(ezxml_t Node,
|
|||
if (0 == strcmp(Prop,"on")) {
|
||||
buffer->tapered_buf = 1;
|
||||
/* Try to dig more properites ...*/
|
||||
buffer->tap_buf_level = GetIntProperty(Node, "tap_buf_level", TRUE, 1);
|
||||
buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 1);
|
||||
buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4);
|
||||
ezxml_set_attr(Node, "tap_buf_level", NULL);
|
||||
ezxml_set_attr(Node, "tap_drive_level", NULL);
|
||||
ezxml_set_attr(Node, "f_per_stage", NULL);
|
||||
} else if (0 == strcmp(FindProperty(Node,"tapered",TRUE),"off")) {
|
||||
buffer->tapered_buf = 0;
|
||||
|
|
@ -752,16 +752,16 @@ static void ProcessSpiceModelPort(ezxml_t Node,
|
|||
ezxml_set_attr(Node, "is_config_enable", NULL);
|
||||
|
||||
/* Check if this port is linked to another spice_model*/
|
||||
port->spice_model_name = my_strdup(FindProperty(Node,"spice_model_name",FALSE));
|
||||
ezxml_set_attr(Node, "spice_model_name", NULL);
|
||||
port->spice_model_name = my_strdup(FindProperty(Node,"circuit_model_name",FALSE));
|
||||
ezxml_set_attr(Node, "circuit_model_name", NULL);
|
||||
|
||||
/* For BL/WL, BLB/WLB ports, we need to get the spice_model for inverters */
|
||||
if ((SPICE_MODEL_PORT_BL == port->type)
|
||||
||(SPICE_MODEL_PORT_WL == port->type)
|
||||
||(SPICE_MODEL_PORT_BLB == port->type)
|
||||
||(SPICE_MODEL_PORT_WLB == port->type)) {
|
||||
port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_spice_model_name", FALSE));
|
||||
ezxml_set_attr(Node, "inv_spice_model_name", NULL);
|
||||
port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_circuit_model_name", FALSE));
|
||||
ezxml_set_attr(Node, "inv_circuit_model_name", NULL);
|
||||
}
|
||||
|
||||
return;
|
||||
|
|
@ -1042,8 +1042,8 @@ static void ProcessSpiceModel(ezxml_t Parent,
|
|||
if (Node) {
|
||||
spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_malloc(sizeof(t_spice_model_pass_gate_logic));
|
||||
/* Find spice_model_name */
|
||||
spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", TRUE));
|
||||
ezxml_set_attr(Node, "spice_model_name", NULL);
|
||||
spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", TRUE));
|
||||
ezxml_set_attr(Node, "circuit_model_name", NULL);
|
||||
FreeNode(Node);
|
||||
} else if ((SPICE_MODEL_MUX == spice_model->type)
|
||||
||(SPICE_MODEL_LUT == spice_model->type)) {
|
||||
|
|
@ -1106,9 +1106,9 @@ void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node,
|
|||
return;
|
||||
}
|
||||
|
||||
cur_sram_inf_orgz->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", required));
|
||||
cur_sram_inf_orgz->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", required));
|
||||
cur_sram_inf_orgz->spice_model = NULL;
|
||||
ezxml_set_attr(Node, "spice_model_name", NULL);
|
||||
ezxml_set_attr(Node, "circuit_model_name", NULL);
|
||||
|
||||
/* read organization type*/
|
||||
Prop = FindProperty(Node, "organization", required);
|
||||
|
|
@ -1501,14 +1501,14 @@ void ProcessSpiceSettings(ezxml_t Parent,
|
|||
ProcessSpiceTechLibTransistors(Parent, &(spice->tech_lib));
|
||||
|
||||
/* module spice models*/
|
||||
Node = FindElement(Parent, "module_spice_models", FALSE);
|
||||
Node = FindElement(Parent, "module_circuit_models", FALSE);
|
||||
if (Node) {
|
||||
spice->num_spice_model = CountChildren(Node, "spice_model", 1);
|
||||
spice->num_spice_model = CountChildren(Node, "circuit_model", 1);
|
||||
/*Alloc*/
|
||||
spice->spice_models = (t_spice_model*)my_malloc(spice->num_spice_model*sizeof(t_spice_model));
|
||||
/* Assign each found spice model*/
|
||||
for (imodel = 0; imodel < spice->num_spice_model; imodel++) {
|
||||
Cur = FindFirstElement(Node, "spice_model", TRUE);
|
||||
Cur = FindFirstElement(Node, "circuit_model", TRUE);
|
||||
ProcessSpiceModel(Cur, &(spice->spice_models[imodel]));
|
||||
FreeNode(Cur);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
|
|||
{ "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */
|
||||
/* Xifan Tang: Bitstream generator */
|
||||
{ "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */
|
||||
{ "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */
|
||||
// { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated
|
||||
/* mrFPGA: Xifan TANG */
|
||||
{"show_sram", OT_SHOW_SRAM},
|
||||
{"show_pass_trans", OT_SHOW_PASS_TRANS},
|
||||
|
|
|
|||
|
|
@ -562,8 +562,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
|
|||
/* Xifan TANG: Bitstream generator */
|
||||
case OT_FPGA_BITSTREAM_GENERATOR:
|
||||
return Args;
|
||||
case OT_FPGA_BITSTREAM_OUTPUT_FILE:
|
||||
return ReadString(Args, &Options->fpga_bitstream_file);
|
||||
// case OT_FPGA_BITSTREAM_OUTPUT_FILE: // AA: temporarily deprecated
|
||||
// return ReadString(Args, &Options->fpga_bitstream_file);
|
||||
/* mrFPGA: Xifan TANG */
|
||||
case OT_SHOW_SRAM:
|
||||
case OT_SHOW_PASS_TRANS:
|
||||
|
|
|
|||
|
|
@ -213,8 +213,8 @@ void vpr_print_usage(void) {
|
|||
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n");
|
||||
/* Xifan Tang: Bitstream generator */
|
||||
vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n");
|
||||
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator <string>\n");
|
||||
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file <string>\n");
|
||||
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n");
|
||||
// vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file <string>\n"); // AA: temporarily deprecated
|
||||
}
|
||||
|
||||
void vpr_init_file_handler() {
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xm
|
|||
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
|
||||
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
|
||||
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
|
||||
vpr_route_chan_width="200"
|
||||
vpr_route_chan_width="300"
|
||||
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
|
||||
ff_path="$vpr_path/VerilogNetlists/ff.v"
|
||||
new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
|
||||
|
|
|
|||
Loading…
Reference in New Issue