*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.*
## Documentation
@@ -31,9 +29,8 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl
## Tutorial
-You can find in the folder **./tutorials**. This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them.
-
-Through this tutorial users can learn how to use the flow and set the dependancies.
-
+You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them.
+Through this tutorial users can learn how to use the flow and set the dependancies.
+The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through trainings and explain folder oraganization as well as referencing tips and used keywords.
diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst
index 839ac7fa9..278bee494 100644
--- a/docs/source/fpga_bitstream/command_line_usage.rst
+++ b/docs/source/fpga_bitstream/command_line_usage.rst
@@ -1,4 +1,14 @@
Command-line Options for FPGA Bitstream Generator
=================================================
-**Under Construction**
\ No newline at end of file
+All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
+
+FPGA-Verilog Supported Option::
+
+ --fpga_bitstream_generator
+
+.. csv-table:: Commmand-line Option of FPGA-Bitstream
+ :header: "Command Options", "Description"
+ :widths: 15, 30
+
+ "--fpga_bitstream_generator", "Turn on the FPGA-Bitstream and output a .bitstream file containing FPGA configuration."
diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst
index dfe34eaea..656b2ecef 100644
--- a/docs/source/fpga_verilog/command_line_usage.rst
+++ b/docs/source/fpga_verilog/command_line_usage.rst
@@ -21,7 +21,6 @@ FPGA-Verilog Supported Options::
:widths: 15, 30
"--fpga_verilog", "Turn on the FPGA-Verilog."
-<<<<<<< HEAD
"--fpga_verilog_dir ", "Specify the directory that all the Verilog files will be outputted to is the destination directory."
"--fpga_verilog_include_timing", "Includes the timings found in the XML file."
"--fpga_verilog_init_sim", "Initializes the simulation for ModelSim."
@@ -30,7 +29,6 @@ FPGA-Verilog Supported Options::
"--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck."
"--fpga_verilog_print_top_auto_testbench \
", "Prints the testbench associated with the given benchmark. Determines the type of autodeck."
-=======
"--fpga_verilog_dir ", "Specify the directory where all the Verilog files will be outputted to. is the destination directory."
"--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file."
"--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case"
@@ -46,8 +44,6 @@ FPGA-Verilog Supported Options::
"--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR"
"--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool"
"--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping"
- "", ""
->>>>>>> f56adc681567b73c7826228641e089482dffc009
.. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are:
diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
index 8dca26477..c4642ed55 100644
--- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
+++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
@@ -187,8 +187,8 @@
-
-
+
+
@@ -198,9 +198,9 @@
10e-12
-
-
-
+
+
+
@@ -209,9 +209,9 @@
10e-12
-
-
-
+
+
+
@@ -220,9 +220,9 @@
10e-12
-
-
-
+
+
+
@@ -231,9 +231,9 @@
10e-12
-
-
-
+
+
+
@@ -242,8 +242,8 @@
10e-12
-
-
+
+
@@ -253,8 +253,8 @@
10e-12
-
-
+
+
@@ -268,8 +268,8 @@
10e-12 5e-12 5e-12
-
-
+
+
@@ -282,141 +282,141 @@
10e-12 10e-12
-
-
+
+
-
-
+
+
-
-
+
+
-
-
+
+
-
+
-
-
+
+
-
-
+
+
-
+
-
-
+
+
-
-
+
+
-
+
-
+
-
+
-
-
-
+
+
+
-
-
+
+
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-
-
-
+
+
+
-
-
-
-
-
-
-
+
+
+
+
+
+
+
-
-
+
+
-
+
-
-
-
+
+
+
-
-
+
+
-
-
-
+
+
+
-
-
+
+
-
+
-
+
-
-
+
+
-
-
+
+
-
-
-
+
+
+
-
+
-
+
-
-
-
+
+
+
@@ -456,7 +456,7 @@
-
+
@@ -473,25 +473,25 @@
2.5x when looking up in Jeff's tables.
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-
+
-
+
-
+
-
+
-
+ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-
+ 1 1 1 1 11 1 1 1
@@ -515,7 +515,7 @@
-
+
@@ -616,7 +616,7 @@
-
-
+
-
+
-
+
-
+
-
+
-
+
-
+
diff --git a/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
new file mode 100644
index 000000000..84d2c3ab3
--- /dev/null
+++ b/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml
@@ -0,0 +1,1139 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 0e-12 0e-12
+
+
+ 10e-12 0e-12 0e-12
+
+
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 1 1 1 1
+ 1 1 1 1
+
+
+
+ 1 1 1
+ 1 1
+
+
+
+ 1 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 235e-12
+ 235e-12
+ 235e-12
+ 235e-12
+ 235e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 195e-12
+ 195e-12
+ 195e-12
+ 195e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+ 261e-12
+ 261e-12
+ 261e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl
index af547d78c..ffe793267 100644
--- a/fpga_flow/scripts/fpga_flow.pl
+++ b/fpga_flow/scripts/fpga_flow.pl
@@ -1358,9 +1358,6 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}";
}
- if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
- $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
- }
if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
}
@@ -1446,6 +1443,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping";
}
+ if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
+ $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
+ }
}
# FPGA Bitstream Generator Options
diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh
index 3ee86966a..7d70423cd 100755
--- a/fpga_flow/tuto_fpga_flow.sh
+++ b/fpga_flow/tuto_fpga_flow.sh
@@ -16,6 +16,9 @@ ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v"
dir_keyword="GENERATED_DIR_KEYWORD"
rm -rf ${pwd_path}/results_OpenPithon
+
+cd ${pwd_path}/arch
+mkdir -p generated # create folder to save rewritten architecture
cd ${pwd_path}/scripts
# Replace keyword in config and architecture files
diff --git a/tutorials/building.md b/tutorials/building.md
index 7f0666313..bc7bc28a9 100644
--- a/tutorials/building.md
+++ b/tutorials/building.md
@@ -40,7 +40,11 @@ OpenFPGA requires all the dependancies listed below:
## Docker
-If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands:
+If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command:
+- docker run lnis/open_fpga:release
+*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".*
+
+Or a container where you can build OpenFPGA yourself can be created with the following commands:
- docker build . -t open_fpga
- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
[*docker download link*](https://www.docker.com/products/docker-desktop)
diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md
index 095325ad7..172f10782 100644
--- a/tutorials/fpga_flow/folder_organization.md
+++ b/tutorials/fpga_flow/folder_organization.md
@@ -17,10 +17,10 @@ In this folder are saved the architecture files. These files are Hardware descri
This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders:
- **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module
- **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module.
-- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#benchmark-list)
+- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#benchmark-list)
## configs
-This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#configuration-file)
+This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#configuration-file)
## scripts
This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.
diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md
index 27c9b1db6..0bbe343a0 100644
--- a/tutorials/fpga_flow/how2use.md
+++ b/tutorials/fpga_flow/how2use.md
@@ -1,7 +1,7 @@
# FPGA flow
This tutorial will help the user to understand how to use OpenFPGA flow.
-During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/folder_organization.md).
+During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md).
## Running fpga_flow.pl
@@ -16,13 +16,13 @@ cd fpga_flow
By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md).
+The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).
There is 3 important things to see:
- All FPGA-Verilog options have been activated
- fpga_flow.pl calls a configuration file through "config_file" variable
- fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable
-## Configuration file
+### Configuration file
In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts:
@@ -64,7 +64,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St
*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
-## Benchmark list
+### Benchmark list
The benchmark folder contains 3 sub-folders:
* **Blif**: contains .blif and .act of benchmarks
@@ -76,3 +76,21 @@ The benchmark list file can contain as many benchmarks as available in the same
top_module/*.v,; where is the number of channel/wire between each block.
*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
+
+
+## Modifying flow
+Once dependancies are understood, we can modify the flow by changing the architecture and the route channel width.
+
+### Experiment
+
+* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial
+* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
+* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List
+* replace "200" with "300" in tuto_benchmark.txt
+* cd OPENFPGAPATHKEYWORD/fpga_flow
+* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
+* ./tuto_fpga_flow.sh
+
+### Explanation
+
+With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed.
diff --git a/tutorials/images/architectures_schematics/frac_lut8.pdf b/tutorials/images/architectures_schematics/frac_lut8.pdf
new file mode 100644
index 000000000..b79821d28
Binary files /dev/null and b/tutorials/images/architectures_schematics/frac_lut8.pdf differ
diff --git a/tutorials/images/architectures_schematics/fract_lut6.pdf b/tutorials/images/architectures_schematics/fract_lut6.pdf
new file mode 100644
index 000000000..2b7d8664e
Binary files /dev/null and b/tutorials/images/architectures_schematics/fract_lut6.pdf differ
diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md
index c6013d6dc..8198fb6da 100644
--- a/tutorials/tutorial_index.md
+++ b/tutorials/tutorial_index.md
@@ -3,8 +3,8 @@
OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.
These tutorials are organized as follow:
-* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md)
-* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md)
+* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
+* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
* Architecture modification
## Folder organization
diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c
index fde8b5472..d852e07dd 100644
--- a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c
+++ b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c
@@ -1052,9 +1052,9 @@ static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,
* We should have a spice_model_name if this mode defines the transistor-level circuit design
* Since this is a leaf node
*/
- pb_type->spice_model_name = my_strdup(FindProperty(Parent, "spice_model_name", FALSE));
+ pb_type->spice_model_name = my_strdup(FindProperty(Parent, "circuit_model_name", FALSE));
pb_type->spice_model = NULL;
- ezxml_set_attr(Parent, "spice_model_name", NULL);
+ ezxml_set_attr(Parent, "circuit_model_name", NULL);
/* Multi-mode CLB support:
* We can read the mode configuration bits if they are defined
*/
@@ -1400,7 +1400,7 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
/* Xifan TANG: SPICE Support */
- Prop = FindProperty(Cur, "spice_model_name", FALSE);
+ Prop = FindProperty(Cur, "circuit_model_name", FALSE);
/* Default spice_model will be define later*/
mode->interconnect[i].spice_model_name = my_strdup(Prop);
mode->interconnect[i].spice_model = NULL;
@@ -1408,7 +1408,7 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {
mode->interconnect[i].fan_in = 0;
mode->interconnect[i].fan_out = 0;
mode->interconnect[i].num_mux = 0;
- ezxml_set_attr(Cur, "spice_model_name", NULL);
+ ezxml_set_attr(Cur, "circuit_model_name", NULL);
/* Get sram offset */
mode->interconnect[i].spice_model_sram_offset = GetIntProperty(Cur, "spice_model_sram_offset", FALSE, 0);
ezxml_set_attr(Cur, "spice_model_sram_offset", NULL);
@@ -3250,9 +3250,9 @@ static void ProcessSegments(INOUTP ezxml_t Parent,
(*Segs)[i].Rmetal = GetFloatProperty(Node, "Rmetal", timing_enabled, 0);
(*Segs)[i].Cmetal = GetFloatProperty(Node, "Cmetal", timing_enabled, 0);
/* Xifan TANG: SPICE Model Support*/
- (*Segs)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE));
+ (*Segs)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE));
(*Segs)[i].spice_model = NULL;
- ezxml_set_attr(Node, "spice_model_name", NULL);
+ ezxml_set_attr(Node, "circuit_model_name", NULL);
/* Get Power info */
/*
(*Segs)[i].Cmetal_per_m = GetFloatProperty(Node, "Cmetal_per_m", FALSE,
@@ -3528,9 +3528,9 @@ static void ProcessSwitches(INOUTP ezxml_t Parent,
FALSE, 1);
/* Xifan TANG: Spice Model Support */
- (*Switches)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE));
+ (*Switches)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE));
(*Switches)[i].spice_model = NULL;
- ezxml_set_attr(Node, "spice_model_name", NULL);
+ ezxml_set_attr(Node, "circuit_model_name", NULL);
/* Xifan TANG : Read in MUX structure*/
/* Default, we use tree */
structure_type = FindProperty(Node, "structure", FALSE);
@@ -3643,9 +3643,9 @@ static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,
/* Spice Model Support: Xifan TANG
* We should have a spice_model_name for this direct connection
*/
- (*Directs)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE));
+ (*Directs)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE));
(*Directs)[i].spice_model = NULL;
- ezxml_set_attr(Node,"spice_model_name",NULL);
+ ezxml_set_attr(Node,"circuit_model_name",NULL);
(*Directs)[i].line = Node->line;
diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
index 82560c359..9e3a511bf 100644
--- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
+++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
@@ -451,8 +451,8 @@ static void ProcessSpiceModelBuffer(ezxml_t Node,
read_spice_model = FALSE;
}
- buffer->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", read_spice_model));
- ezxml_set_attr(Node, "spice_model_name", NULL);
+ buffer->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", read_spice_model));
+ ezxml_set_attr(Node, "circuit_model_name", NULL);
/*Find Type*/
Prop = my_strdup(FindProperty(Node, "topology", read_buf_info));
@@ -475,9 +475,9 @@ static void ProcessSpiceModelBuffer(ezxml_t Node,
if (0 == strcmp(Prop,"on")) {
buffer->tapered_buf = 1;
/* Try to dig more properites ...*/
- buffer->tap_buf_level = GetIntProperty(Node, "tap_buf_level", TRUE, 1);
+ buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 1);
buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4);
- ezxml_set_attr(Node, "tap_buf_level", NULL);
+ ezxml_set_attr(Node, "tap_drive_level", NULL);
ezxml_set_attr(Node, "f_per_stage", NULL);
} else if (0 == strcmp(FindProperty(Node,"tapered",TRUE),"off")) {
buffer->tapered_buf = 0;
@@ -752,16 +752,16 @@ static void ProcessSpiceModelPort(ezxml_t Node,
ezxml_set_attr(Node, "is_config_enable", NULL);
/* Check if this port is linked to another spice_model*/
- port->spice_model_name = my_strdup(FindProperty(Node,"spice_model_name",FALSE));
- ezxml_set_attr(Node, "spice_model_name", NULL);
+ port->spice_model_name = my_strdup(FindProperty(Node,"circuit_model_name",FALSE));
+ ezxml_set_attr(Node, "circuit_model_name", NULL);
/* For BL/WL, BLB/WLB ports, we need to get the spice_model for inverters */
if ((SPICE_MODEL_PORT_BL == port->type)
||(SPICE_MODEL_PORT_WL == port->type)
||(SPICE_MODEL_PORT_BLB == port->type)
||(SPICE_MODEL_PORT_WLB == port->type)) {
- port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_spice_model_name", FALSE));
- ezxml_set_attr(Node, "inv_spice_model_name", NULL);
+ port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_circuit_model_name", FALSE));
+ ezxml_set_attr(Node, "inv_circuit_model_name", NULL);
}
return;
@@ -1042,8 +1042,8 @@ static void ProcessSpiceModel(ezxml_t Parent,
if (Node) {
spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_malloc(sizeof(t_spice_model_pass_gate_logic));
/* Find spice_model_name */
- spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", TRUE));
- ezxml_set_attr(Node, "spice_model_name", NULL);
+ spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", TRUE));
+ ezxml_set_attr(Node, "circuit_model_name", NULL);
FreeNode(Node);
} else if ((SPICE_MODEL_MUX == spice_model->type)
||(SPICE_MODEL_LUT == spice_model->type)) {
@@ -1106,9 +1106,9 @@ void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node,
return;
}
- cur_sram_inf_orgz->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", required));
+ cur_sram_inf_orgz->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", required));
cur_sram_inf_orgz->spice_model = NULL;
- ezxml_set_attr(Node, "spice_model_name", NULL);
+ ezxml_set_attr(Node, "circuit_model_name", NULL);
/* read organization type*/
Prop = FindProperty(Node, "organization", required);
@@ -1501,14 +1501,14 @@ void ProcessSpiceSettings(ezxml_t Parent,
ProcessSpiceTechLibTransistors(Parent, &(spice->tech_lib));
/* module spice models*/
- Node = FindElement(Parent, "module_spice_models", FALSE);
+ Node = FindElement(Parent, "module_circuit_models", FALSE);
if (Node) {
- spice->num_spice_model = CountChildren(Node, "spice_model", 1);
+ spice->num_spice_model = CountChildren(Node, "circuit_model", 1);
/*Alloc*/
spice->spice_models = (t_spice_model*)my_malloc(spice->num_spice_model*sizeof(t_spice_model));
/* Assign each found spice model*/
for (imodel = 0; imodel < spice->num_spice_model; imodel++) {
- Cur = FindFirstElement(Node, "spice_model", TRUE);
+ Cur = FindFirstElement(Node, "circuit_model", TRUE);
ProcessSpiceModel(Cur, &(spice->spice_models[imodel]));
FreeNode(Cur);
}
diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c
index a0d765a89..78b956ce3 100644
--- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c
+++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c
@@ -102,7 +102,7 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */
/* Xifan Tang: Bitstream generator */
{ "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */
- { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */
+ // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated
/* mrFPGA: Xifan TANG */
{"show_sram", OT_SHOW_SRAM},
{"show_pass_trans", OT_SHOW_PASS_TRANS},
diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c
index b90b90f4f..108e9d355 100644
--- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c
+++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c
@@ -562,8 +562,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
/* Xifan TANG: Bitstream generator */
case OT_FPGA_BITSTREAM_GENERATOR:
return Args;
- case OT_FPGA_BITSTREAM_OUTPUT_FILE:
- return ReadString(Args, &Options->fpga_bitstream_file);
+// case OT_FPGA_BITSTREAM_OUTPUT_FILE: // AA: temporarily deprecated
+// return ReadString(Args, &Options->fpga_bitstream_file);
/* mrFPGA: Xifan TANG */
case OT_SHOW_SRAM:
case OT_SHOW_PASS_TRANS:
diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c
index 023b2df92..7d1730883 100644
--- a/vpr7_x2p/vpr/SRC/base/vpr_api.c
+++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c
@@ -213,8 +213,8 @@ void vpr_print_usage(void) {
vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n");
/* Xifan Tang: Bitstream generator */
vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n");
- vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator \n");
- vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n");
+ vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n");
+// vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n"); // AA: temporarily deprecated
}
void vpr_init_file_handler() {
diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh
index 8007363cf..190ae5523 100755
--- a/vpr7_x2p/vpr/regression_verilog.sh
+++ b/vpr7_x2p/vpr/regression_verilog.sh
@@ -14,7 +14,7 @@ arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xm
blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif"
act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act "
verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v"
-vpr_route_chan_width="200"
+vpr_route_chan_width="300"
fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts"
ff_path="$vpr_path/VerilogNetlists/ff.v"
new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"