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Correct verilog syntax error in autocheck testbench

This commit is contained in:
Aur??Lien ALACCHI 2018-12-08 17:40:23 -07:00
parent d716b67e23
commit 10866d1852
1 changed files with 3 additions and 3 deletions
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6
vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_autocheck_tb.c
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@ -543,8 +543,8 @@ void dump_verilog_top_auto_testbench_ports(FILE* fp,
gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx); gio_inout_prefix, iopad_verilog_model->prefix, iopad_idx);
// AA: Generate wire and reg to autocheck with benchmark // AA: Generate wire and reg to autocheck with benchmark
if(VPACK_OUTPAD == logical_block[iblock].type) { if(VPACK_OUTPAD == logical_block[iblock].type) {
fprintf(fp, "wire %s_benchmark\n", logical_block[iblock].name); fprintf(fp, "wire %s_benchmark;\n", logical_block[iblock].name);
fprintf(fp, "reg %s_verification\n", logical_block[iblock].name); fprintf(fp, "reg %s_verification;\n", logical_block[iblock].name);
} }
} }
@ -594,8 +594,8 @@ void dump_verilog_top_auto_testbench_check(FILE* fp){
fprintf(fp, " %s_verification <= %s_benchmark ^ %s_%s_%d_ ;\n", logical_block[iblock].name, logical_block[iblock].name, logical_block[iblock].name, gio_inout_prefix, iopad_idx); fprintf(fp, " %s_verification <= %s_benchmark ^ %s_%s_%d_ ;\n", logical_block[iblock].name, logical_block[iblock].name, logical_block[iblock].name, gio_inout_prefix, iopad_idx);
} }
} }
fprintf(fp, " end\n\n");
} }
fprintf(fp, " end\n\n");
for (iblock = 0; iblock < num_logical_blocks; iblock++) { for (iblock = 0; iblock < num_logical_blocks; iblock++) {
if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) { if (iopad_verilog_model == logical_block[iblock].mapped_spice_model) {
iopad_idx = logical_block[iblock].mapped_spice_model_index; iopad_idx = logical_block[iblock].mapped_spice_model_index;