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Update dpram16k.v

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Yunus Emre ERYILMAZ 2022-10-27 08:28:58 +03:00 committed by GitHub
parent 74568b13a2
commit 0fe3bd36b6
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1 changed files with 5 additions and 5 deletions
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openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
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@ -9,8 +9,8 @@ module dpram_512x32 (
input clk, input clk,
input wen, input wen,
input ren, input ren,
input[0:9] waddr, input[0:8] waddr,
input[0:9] raddr, input[0:8] raddr,
input[0:31] d_in, input[0:31] d_in,
output[0:31] d_out ); output[0:31] d_out );
@ -29,14 +29,14 @@ endmodule
module dpram_512x32_core ( module dpram_512x32_core (
input wclk, input wclk,
input wen, input wen,
input[0:9] waddr, input[0:8] waddr,
input[0:31] data_in, input[0:31] data_in,
input rclk, input rclk,
input ren, input ren,
input[0:9] raddr, input[0:8] raddr,
output[0:31] d_out ); output[0:31] d_out );
reg[0:31] ram[0:1023]; reg[0:31] ram[0:511];
reg[0:31] internal; reg[0:31] internal;
assign d_out = internal; assign d_out = internal;