diff --git a/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
index 386b38da5..e6e7069c0 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dpram16k.v
@@ -9,8 +9,8 @@ module dpram_512x32 (
 	input clk,
 	input wen,
 	input ren,
-	input[0:9] waddr,
-	input[0:9] raddr,
+	input[0:8] waddr,
+	input[0:8] raddr,
 	input[0:31] d_in,
 	output[0:31] d_out );
 
@@ -29,14 +29,14 @@ endmodule
 module dpram_512x32_core (
 	input wclk,
 	input wen,
-	input[0:9] waddr,
+	input[0:8] waddr,
 	input[0:31] data_in,
 	input rclk,
 	input ren,
-	input[0:9] raddr,
+	input[0:8] raddr,
 	output[0:31] d_out );
 
-	reg[0:31] ram[0:1023];
+	reg[0:31] ram[0:511];
 	reg[0:31] internal;
 
 	assign d_out = internal;