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Bumping up yosys submodule as an option (-verilog) is added to write verilog file

This commit is contained in:
Lalit Sharma 2021-02-01 13:43:31 +05:30
parent 186a0cadfb
commit 0f287fb539
1 changed files with 1 additions and 1 deletions
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2
yosys

@ -1 +1 @@
Subproject commit e6ff764e4976a22ce855a4a58c42be8f74f3a8c6
Subproject commit 77570b6e0f97f1923ebafd51ebfc9d9224a2f4cf