From 0f287fb53999b6f6f1f8be949ffc105551152162 Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Mon, 1 Feb 2021 13:43:31 +0530
Subject: [PATCH] Bumping up yosys submodule as an option (-verilog) is added
 to write verilog file

---
 yosys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/yosys b/yosys
index e6ff764e4..77570b6e0 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit e6ff764e4976a22ce855a4a58c42be8f74f3a8c6
+Subproject commit 77570b6e0f97f1923ebafd51ebfc9d9224a2f4cf