[FPGA-Verilog] code format fix

openfpga/src/fpga_spice/spice_submodule.cpp

@@ -26,10 +26,10 @@ namespace openfpga {
  * Top-level function to generate primitive modules:
  * 1. Transistor wrapper
  * 2. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
- * 3. TODO: Routing multiplexers
+ * 3. Routing multiplexers
  * 4. TODO: Local encoders for routing multiplexers
  * 5. Wires
- * 6. TODO: Configuration memory blocks
+ * 6. Configuration memory blocks
  ********************************************************************/
 int print_spice_submodule(NetlistManager& netlist_manager,
                           const ModuleManager& module_manager,
@@ -77,6 +77,8 @@ int print_spice_submodule(NetlistManager& netlist_manager,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* TODO: local decoders for routing multiplexers */
+
   /* Routing multiplexers */
   status = print_spice_submodule_muxes(netlist_manager,
                                        module_manager,
@@ -112,6 +114,8 @@ int print_spice_submodule(NetlistManager& netlist_manager,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* TODO: architecture decoders */
+
   return status;
 }
 

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -60,8 +60,7 @@ namespace openfpga
                          const DeviceContext &device_ctx,
                          const VprDeviceAnnotation &device_annotation,
                          const DeviceRRGSB &device_rr_gsb,
-                           const FabricVerilogOption &options)
+                         const FabricVerilogOption &options) {
-  {
 
   vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
@@ -99,16 +98,13 @@ namespace openfpga
                           options);
 
   /* Generate routing blocks */
-    if (true == options.compress_routing())
+  if (true == options.compress_routing()) {
-    {
     print_verilog_unique_routing_modules(netlist_manager,
                                          const_cast<const ModuleManager &>(module_manager),
                                          device_rr_gsb,
                                          rr_dir_path,
                                          options.explicit_port_mapping());
-    }
+  } else {
-    else
-    {
     VTR_ASSERT(false == options.compress_routing());
     print_verilog_flatten_routing_modules(netlist_manager,
                                           const_cast<const ModuleManager &>(module_manager),
@@ -161,8 +157,7 @@ namespace openfpga
                             const CircuitLibrary &circuit_lib,
                             const SimulationSetting &simulation_setting,
                             const e_config_protocol_type &config_protocol_type,
-                              const VerilogTestbenchOption &options)
+                            const VerilogTestbenchOption &options) {
-  {
 
   vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n");
 
@@ -183,8 +178,7 @@ namespace openfpga
   std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(circuit_lib);
 
   /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */
-    if (true == options.print_formal_verification_top_netlist())
+  if (true == options.print_formal_verification_top_netlist()) {
-    {
     std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX);
     print_verilog_preconfig_top_module(module_manager, bitstream_manager,
                                        circuit_lib, global_ports,
@@ -195,8 +189,7 @@ namespace openfpga
                                        options.explicit_port_mapping());
   }
 
-    if (true == options.print_preconfig_top_testbench())
+  if (true == options.print_preconfig_top_testbench()) {
-    {
     /* Generate top-level testbench using random vectors */
     std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
     print_verilog_random_top_testbench(netlist_name,
@@ -208,8 +201,7 @@ namespace openfpga
   }
 
   /* Generate full testbench for verification, including configuration phase and operating phase */
-    if (true == options.print_top_testbench())
+  if (true == options.print_top_testbench()) {
-    {
     std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
     print_verilog_top_testbench(module_manager,
                                 bitstream_manager, fabric_bitstream,
@@ -225,8 +217,7 @@ namespace openfpga
   }
 
   /* Generate exchangeable files which contains simulation settings */
-    if (true == options.print_simulation_ini())
+  if (true == options.print_simulation_ini()) {
-    {
     std::string simulation_ini_file_name = options.simulation_ini_path();
     VTR_ASSERT(true != options.simulation_ini_path().empty());
     print_verilog_simulation_info(simulation_ini_file_name,