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Revert to the use of sprintf instead std::string. Have no idea why string is not working

This commit is contained in:
tangxifan 2019-06-07 18:54:57 -06:00
parent 44ce0e8834
commit 0f1ed19ad0
6 changed files with 29 additions and 26 deletions
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12
fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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@ -180,7 +180,7 @@
</input> </input>
</stimulate> </stimulate>
</parameters> </parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/> <tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M"> <transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/> <nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/> <pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
@ -330,7 +330,7 @@
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
</spice_model> </spice_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/ff.v"> <spice_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/> <input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/> <output_buffer exist="on" spice_model_name="INV1X"/>
@ -372,7 +372,7 @@
<port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/> <port type="sram" prefix="mode" size="2" mode_select="true" spice_model_name="sc_dff_compact" default_val="1"/>
</spice_model> </spice_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<spice_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/ff.v"> <spice_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/ff.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/> <input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/> <output_buffer exist="on" spice_model_name="INV1X"/>
@ -384,7 +384,7 @@
<port type="output" prefix="Qb" size="1"/> <port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/> <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
</spice_model> </spice_model>
<spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/io.v"> <spice_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/> <input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/> <output_buffer exist="on" spice_model_name="INV1X"/>
@ -397,7 +397,7 @@
<port type="output" prefix="inpad" size="1"/> <port type="output" prefix="inpad" size="1"/>
</spice_model> </spice_model>
<!-- Hard logic definition for heterogenous blocks --> <!-- Hard logic definition for heterogenous blocks -->
<spice_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v"> <spice_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/adder.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/> <input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/> <output_buffer exist="on" spice_model_name="INV1X"/>
@ -407,7 +407,7 @@
<port type="output" prefix="sumout" size="1"/> <port type="output" prefix="sumout" size="1"/>
<port type="output" prefix="cout" size="1"/> <port type="output" prefix="cout" size="1"/>
</spice_model> </spice_model>
<spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/sram.v"> <spice_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/sram.v">
<design_technology type="cmos"/> <design_technology type="cmos"/>
<input_buffer exist="on" spice_model_name="INV1X"/> <input_buffer exist="on" spice_model_name="INV1X"/>
<output_buffer exist="on" spice_model_name="INV1X"/> <output_buffer exist="on" spice_model_name="INV1X"/>

2
fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power
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@ -1,5 +1,5 @@
----------------------------------- Summary ------------------------------------ ----------------------------------- Summary ------------------------------------
Circuit: /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes Circuit: /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes
Architecture: k6_N10_sram_chain_HC_template.xml Architecture: k6_N10_sram_chain_HC_template.xml
Technology (nm): 45 Technology (nm): 45
Voltage: 0.90 Voltage: 0.90

35
vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp
View File

@ -1335,16 +1335,20 @@ const char* RRGSB::gen_sb_verilog_module_name() const {
std::string x_str = std::to_string(get_sb_x()); std::string x_str = std::to_string(get_sb_x());
std::string y_str = std::to_string(get_sb_y()); std::string y_str = std::to_string(get_sb_y());
std::string ret = "sb_" + x_str + "__" + y_str + "_"; std::string ret;
ret.append("sb_");
ret.append(x_str);
ret.append("__");
ret.append(y_str);
ret.append("_");
return ret.c_str(); return ret.c_str();
} }
const char* RRGSB::gen_sb_verilog_instance_name() const { const char* RRGSB::gen_sb_verilog_instance_name() const {
std::string x_str = std::to_string(get_sb_x());
std::string y_str = std::to_string(get_sb_y());
std::string ret = "sb_" + x_str + "__" + y_str + "__0_"; std::string ret(gen_sb_verilog_module_name());
ret.append("_0_");
return ret.c_str(); return ret.c_str();
} }
@ -1353,27 +1357,26 @@ const char* RRGSB::gen_sb_verilog_instance_name() const {
const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const { const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const {
Side side_manager(side); Side side_manager(side);
std::string x_str = std::to_string(get_sb_x()); std::string seg_id_str(std::to_string(seg_id));
std::string y_str = std::to_string(get_sb_y());
std::string seg_id_str = std::to_string(seg_id);
std::string side_str(side_manager.to_string()); std::string side_str(side_manager.to_string());
std::string prefix(gen_sb_verilog_module_name());
char* ret = NULL;
std::string ret = "sb_" + x_str + "__" + y_str + "__" + side_str + "_seg_" + seg_id_str + "_"; ret = (char*) my_malloc (prefix.length() + 1 + side_str.length() + 5 + seg_id_str.length() + 1 + 1);
sprintf(ret, "%s_%s_seg_%s_", prefix.c_str(), side_str.c_str(), seg_id_str.c_str());
return ret.c_str(); return ret;
} }
const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const { const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const {
Side side_manager(side);
std::string x_str = std::to_string(get_sb_x()); std::string prefix(gen_sb_verilog_side_module_name(side, seg_id));
std::string y_str = std::to_string(get_sb_y());
std::string seg_id_str = std::to_string(seg_id);
std::string side_str(side_manager.to_string());
std::string ret = "sb_" + x_str + "__" + y_str + "__" + side_str + "_seg_" + seg_id_str + "__0_"; char* ret = NULL;
ret = (char*) my_malloc (prefix.length() + 3 + 1);
sprintf(ret, "%s_0_", prefix.c_str());
return ret.c_str(); return ret;
} }
/* Public Accessors Verilog writer */ /* Public Accessors Verilog writer */

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
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@ -2627,7 +2627,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info
dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_lsb,
cur_sb_info->conf_bits_msb - 1, cur_sb_info->conf_bits_msb - 1,
VERILOG_PORT_OUTPUT); VERILOG_PORT_INPUT);
fprintf(fp, "\n"); fprintf(fp, "\n");
fprintf(fp, "`endif\n"); fprintf(fp, "`endif\n");
} }

2
vpr7_x2p/vpr/VerilogNetlists/ff.v
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@ -5,7 +5,7 @@
// Coder : Xifan TANG // Coder : Xifan TANG
//----------------------------------------------------- //-----------------------------------------------------
//------ Include defines: preproc flags ----- //------ Include defines: preproc flags -----
`include "OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v" `include "/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v"
module static_dff ( module static_dff (
/* Global ports go first */ /* Global ports go first */
input set, // set input input set, // set input

2
vpr7_x2p/vpr/regression_verilog.sh
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@ -4,7 +4,7 @@
# Set variables # Set variables
# For FPGA-Verilog ONLY # For FPGA-Verilog ONLY
benchmark="test_modes" benchmark="test_modes"
OpenFPGA_path="OPENFPGAPATHKEYWORD" OpenFPGA_path="/research/ece/lnis/USERS/tang/github/OpenFPGA"
verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirname="${benchmark}_Verilog"
verilog_output_dirpath="$PWD" verilog_output_dirpath="$PWD"
tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"