start reworking the openfpga tool documentation

docs/source/fpga_bitstream/command_line_usage.rst

@@ -1,5 +1,5 @@
-Command-line Options for FPGA Bitstream Generator
+Command-line Options
-=================================================
+~~~~~~~~~~~~~~~~~~~~
 
 All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
 

docs/source/fpga_bitstream/file_organization.rst

@@ -1,5 +1,5 @@
 Bistream Output File Format
-============================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 FPGA-Bitstream can generate two types of bitstreams:
 * Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: 

docs/source/fpga_bitstream/index.rst

@@ -1,3 +1,5 @@
+FPGA-Bitstream
+--------------
 .. _fpga_bitstream:
    FPGA-Bitstream
  

docs/source/fpga_spice/command_line_usage.rst

@@ -1,5 +1,5 @@
-Command-line Options for FPGA SPICE Generator
+Command-line Options
-=================================================
+~~~~~~~~~~~~~~~~~~~~
 All the command line options of FPGA-SPICE can be shown by calling the help menu of VPR. Here are all the FPGA-SPICE-related options that you can find:
 
 FPGA-SPICE Supported Options::

docs/source/fpga_spice/customize_subckt.rst

@@ -1,5 +1,5 @@
 Create Customized SPICE Modules
-===============================
+-------------------------------
 To make sure the customized SPICE netlists can be correctly included in FPGA-SPICE, the following rules should be fully respected:
 
 1.    The customized SPICE netlists could contain multiple sub-circuits but the names of these sub-circuits should not be conflicted with any reserved words.. Here is an example of defining a sub-circuit in SPICE netlists. The <subckt_name> should be a unique one, which should not be conflicted with any reserved words.

docs/source/fpga_spice/file_organization.rst

@@ -1,5 +1,5 @@
 Hierarchy of SPICE Output Files
-===============================
+-------------------------------
 
 All the generated SPICE netlists are located in the <spice_dir> as you specify in the command-line options.
 Under the <spice_dir>, FPGA-SPICE creates a number of folders:  include, subckt, lut_tb, dff_tb, grid_tb, pb_mux_tb, cb_mux_tb, sb_mux_tb, top_tb, results. Under the <spice_dir>, FPGA-SPICE also creates a shell script called run_hspice_sim.sh, which run all the simulations for all the testbenches.

docs/source/fpga_spice/index.rst

@@ -1,7 +1,10 @@
+FPGA-SPICE
+----------
 .. _fpga_spice:
    FPGA-SPICE
  
 .. toctree::
+   :maxdepth: 2
   
    command_line_usage
 

docs/source/fpga_spice/spice_simulation.rst

@@ -1,5 +1,5 @@
 Run SPICE simulation
-====================
+--------------------
 
 * Simulation results 
 

docs/source/fpga_verilog/command_line_usage.rst

@@ -1,5 +1,5 @@
-Command-line Options for FPGA-Verilog Generator
+Command-line Options
-=================================================
+~~~~~~~~~~~~~~~~~~~~
 
 All the command line options of FPGA-Verilog can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find:
 

docs/source/fpga_verilog/file_organization.rst

@@ -1,5 +1,5 @@
 Hierarchy of Verilog Output Files
-=================================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 All the generated Verilog Netlists are located in the <verilog_dir>/SRC as you specify in the command-line options. Under the <verilog_dir>/SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. 
 

docs/source/fpga_verilog/func_verify.rst

@@ -1,5 +1,5 @@
 Perform Functionality Verification
-==================================
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 If the --fpga_verilog_print_modelsim_autodeck option is selected, it is possible to directly generate scripts for Modelsim. Inside of the Verilog directory specified with --fpga_verilog_dir can be found name_runsim.tcl scripts which perform the functional verification onto the FPGA generated. 
 

docs/source/fpga_verilog/index.rst

@@ -1,3 +1,5 @@
+FPGA-Verilog
+------------
 .. _fpga_verilog:
    FPGA-Verilog
  

docs/source/fpga_verilog/sc_flow.rst

@@ -1,5 +1,5 @@
 From Verilog to Layout
-======================
+~~~~~~~~~~~~~~~~~~~~~~
 
 The generated Verilog code can be used through a semi-custom design flow to generate the layout.