From 0da6f00af5b115a96ba75d191d567e48ee4c6e8f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 10 Mar 2020 17:29:35 -0600 Subject: [PATCH] start reworking the openfpga tool documentation --- docs/source/fpga_bitstream/command_line_usage.rst | 4 ++-- docs/source/fpga_bitstream/file_organization.rst | 2 +- docs/source/fpga_bitstream/index.rst | 2 ++ docs/source/fpga_spice/command_line_usage.rst | 4 ++-- docs/source/fpga_spice/customize_subckt.rst | 2 +- docs/source/fpga_spice/file_organization.rst | 2 +- docs/source/fpga_spice/index.rst | 3 +++ docs/source/fpga_spice/spice_simulation.rst | 2 +- docs/source/fpga_verilog/command_line_usage.rst | 4 ++-- docs/source/fpga_verilog/file_organization.rst | 2 +- docs/source/fpga_verilog/func_verify.rst | 2 +- docs/source/fpga_verilog/index.rst | 2 ++ docs/source/fpga_verilog/sc_flow.rst | 2 +- 13 files changed, 20 insertions(+), 13 deletions(-) diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst index 278bee494..43fffe97e 100644 --- a/docs/source/fpga_bitstream/command_line_usage.rst +++ b/docs/source/fpga_bitstream/command_line_usage.rst @@ -1,5 +1,5 @@ -Command-line Options for FPGA Bitstream Generator -================================================= +Command-line Options +~~~~~~~~~~~~~~~~~~~~ All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find: diff --git a/docs/source/fpga_bitstream/file_organization.rst b/docs/source/fpga_bitstream/file_organization.rst index 1cc152d40..c8476d1f9 100644 --- a/docs/source/fpga_bitstream/file_organization.rst +++ b/docs/source/fpga_bitstream/file_organization.rst @@ -1,5 +1,5 @@ Bistream Output File Format -============================ +~~~~~~~~~~~~~~~~~~~~~~~~~~~ FPGA-Bitstream can generate two types of bitstreams: * Generic bitstreams, where configuration bits are organized out-of-order in a database. We output the generic bitstream to a XML format, which is easy to debug. As shown in the following XML code, configuration bits are organized block by block, where each block could be a LUT, a routing multiplexer `etc`. Each ``bitstream_block`` includes two sets of information: diff --git a/docs/source/fpga_bitstream/index.rst b/docs/source/fpga_bitstream/index.rst index 6380cc322..9fb992ace 100644 --- a/docs/source/fpga_bitstream/index.rst +++ b/docs/source/fpga_bitstream/index.rst @@ -1,3 +1,5 @@ +FPGA-Bitstream +-------------- .. _fpga_bitstream: FPGA-Bitstream diff --git a/docs/source/fpga_spice/command_line_usage.rst b/docs/source/fpga_spice/command_line_usage.rst index 129c05e05..e7c261ab3 100644 --- a/docs/source/fpga_spice/command_line_usage.rst +++ b/docs/source/fpga_spice/command_line_usage.rst @@ -1,5 +1,5 @@ -Command-line Options for FPGA SPICE Generator -================================================= +Command-line Options +~~~~~~~~~~~~~~~~~~~~ All the command line options of FPGA-SPICE can be shown by calling the help menu of VPR. Here are all the FPGA-SPICE-related options that you can find: FPGA-SPICE Supported Options:: diff --git a/docs/source/fpga_spice/customize_subckt.rst b/docs/source/fpga_spice/customize_subckt.rst index fca30912f..e62d3578b 100644 --- a/docs/source/fpga_spice/customize_subckt.rst +++ b/docs/source/fpga_spice/customize_subckt.rst @@ -1,5 +1,5 @@ Create Customized SPICE Modules -=============================== +------------------------------- To make sure the customized SPICE netlists can be correctly included in FPGA-SPICE, the following rules should be fully respected: 1. The customized SPICE netlists could contain multiple sub-circuits but the names of these sub-circuits should not be conflicted with any reserved words.. Here is an example of defining a sub-circuit in SPICE netlists. The should be a unique one, which should not be conflicted with any reserved words. diff --git a/docs/source/fpga_spice/file_organization.rst b/docs/source/fpga_spice/file_organization.rst index 4a099bc95..f9a2f8575 100644 --- a/docs/source/fpga_spice/file_organization.rst +++ b/docs/source/fpga_spice/file_organization.rst @@ -1,5 +1,5 @@ Hierarchy of SPICE Output Files -=============================== +------------------------------- All the generated SPICE netlists are located in the as you specify in the command-line options. Under the , FPGA-SPICE creates a number of folders: include, subckt, lut_tb, dff_tb, grid_tb, pb_mux_tb, cb_mux_tb, sb_mux_tb, top_tb, results. Under the , FPGA-SPICE also creates a shell script called run_hspice_sim.sh, which run all the simulations for all the testbenches. diff --git a/docs/source/fpga_spice/index.rst b/docs/source/fpga_spice/index.rst index c9c04568a..f09b1bea0 100644 --- a/docs/source/fpga_spice/index.rst +++ b/docs/source/fpga_spice/index.rst @@ -1,7 +1,10 @@ +FPGA-SPICE +---------- .. _fpga_spice: FPGA-SPICE .. toctree:: + :maxdepth: 2 command_line_usage diff --git a/docs/source/fpga_spice/spice_simulation.rst b/docs/source/fpga_spice/spice_simulation.rst index f0aa7e2d0..29173d0b8 100644 --- a/docs/source/fpga_spice/spice_simulation.rst +++ b/docs/source/fpga_spice/spice_simulation.rst @@ -1,5 +1,5 @@ Run SPICE simulation -==================== +-------------------- * Simulation results diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index 656b2ecef..2e963319d 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -1,5 +1,5 @@ -Command-line Options for FPGA-Verilog Generator -================================================= +Command-line Options +~~~~~~~~~~~~~~~~~~~~ All the command line options of FPGA-Verilog can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find: diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/fpga_verilog/file_organization.rst index 0c223a822..181be2295 100644 --- a/docs/source/fpga_verilog/file_organization.rst +++ b/docs/source/fpga_verilog/file_organization.rst @@ -1,5 +1,5 @@ Hierarchy of Verilog Output Files -================================= +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ All the generated Verilog Netlists are located in the /SRC as you specify in the command-line options. Under the /SRC, FPGA-Verilog creates the top file name_top.v and some folders: lb (logic blocks), routing and sub_modules. diff --git a/docs/source/fpga_verilog/func_verify.rst b/docs/source/fpga_verilog/func_verify.rst index cbb8af96c..a21a01c1e 100644 --- a/docs/source/fpga_verilog/func_verify.rst +++ b/docs/source/fpga_verilog/func_verify.rst @@ -1,5 +1,5 @@ Perform Functionality Verification -================================== +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ If the --fpga_verilog_print_modelsim_autodeck option is selected, it is possible to directly generate scripts for Modelsim. Inside of the Verilog directory specified with --fpga_verilog_dir can be found name_runsim.tcl scripts which perform the functional verification onto the FPGA generated. diff --git a/docs/source/fpga_verilog/index.rst b/docs/source/fpga_verilog/index.rst index 2ea55c478..db8740fa0 100644 --- a/docs/source/fpga_verilog/index.rst +++ b/docs/source/fpga_verilog/index.rst @@ -1,3 +1,5 @@ +FPGA-Verilog +------------ .. _fpga_verilog: FPGA-Verilog diff --git a/docs/source/fpga_verilog/sc_flow.rst b/docs/source/fpga_verilog/sc_flow.rst index 03a9069fe..f89d71db2 100644 --- a/docs/source/fpga_verilog/sc_flow.rst +++ b/docs/source/fpga_verilog/sc_flow.rst @@ -1,5 +1,5 @@ From Verilog to Layout -====================== +~~~~~~~~~~~~~~~~~~~~~~ The generated Verilog code can be used through a semi-custom design flow to generate the layout.