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[Engine] Bug fix for the undriven WLR nets in top-level modules

This commit is contained in:
tangxifan 2021-09-28 11:53:38 -07:00
parent 4400dae108
commit 0d72e115ac
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fabric/build_top_module_memory_bank.cpp
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@ -907,8 +907,8 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager,
/* Optional: If we have WLR port, we should add a read-back port */
if (!circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLR).empty()) {
BasicPort readback_port(std::string(MEMORY_WLR_PORT_NAME), wl_size);
module_manager.add_port(module_id, readback_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort wlr_port(generate_regional_blwl_port_name(std::string(MEMORY_WLR_PORT_NAME), config_region), wl_size);
module_manager.add_port(module_id, wlr_port, ModuleManager::MODULE_INPUT_PORT);
}
}
break;