From 0d72e115ace9e79301bd66c600646d1f98770b2d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Sep 2021 11:53:38 -0700
Subject: [PATCH] [Engine] Bug fix for the undriven WLR nets in top-level
 modules

---
 openfpga/src/fabric/build_top_module_memory_bank.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp
index 63cf7ea77..188efd2f4 100644
--- a/openfpga/src/fabric/build_top_module_memory_bank.cpp
+++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp
@@ -907,8 +907,8 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager,
 
         /* Optional: If we have WLR port, we should add a read-back port */
         if (!circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLR).empty()) {
-          BasicPort readback_port(std::string(MEMORY_WLR_PORT_NAME), wl_size);
-          module_manager.add_port(module_id, readback_port, ModuleManager::MODULE_INPUT_PORT);
+          BasicPort wlr_port(generate_regional_blwl_port_name(std::string(MEMORY_WLR_PORT_NAME), config_region), wl_size);
+          module_manager.add_port(module_id, wlr_port, ModuleManager::MODULE_INPUT_PORT);
         }
       }
       break;