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bug fixing and spot critical bugs in directlist parser

This commit is contained in:
tangxifan 2019-06-23 20:52:38 -06:00
parent cdd4af9c58
commit 0d62661c71
4 changed files with 28 additions and 8 deletions
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16
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp
View File

@ -858,6 +858,17 @@ void build_rr_graph_direct_connections(t_rr_graph* rr_graph,
return; return;
} }
/************************************************************************
* Reset driver switch of a rr_graph
***********************************************************************/
static
void clear_rr_graph_driver_switch(const t_rr_graph* rr_graph) {
for (int inode = 0; inode < rr_graph->num_rr_nodes; ++inode) {
rr_graph->rr_node[inode].driver_switch = 0;
}
return;
}
/************************************************************************ /************************************************************************
* Main function of this file * Main function of this file
* Builder for a detailed uni-directional tileable rr_graph * Builder for a detailed uni-directional tileable rr_graph
@ -1038,6 +1049,9 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types,
vpr_printf(TIO_MESSAGE_INFO, vpr_printf(TIO_MESSAGE_INFO,
"%lu edges of RR graph built.\n", num_edges); "%lu edges of RR graph built.\n", num_edges);
/* Clear driver switches of the rr_graph */
clear_rr_graph_driver_switch(&rr_graph);
/************************************************************************ /************************************************************************
* 8. Allocate external data structures * 8. Allocate external data structures
* a. cost_index * a. cost_index
@ -1046,7 +1060,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types,
/* We set global variables for rr_nodes here, they will be updated by rr_graph_external */ /* We set global variables for rr_nodes here, they will be updated by rr_graph_external */
num_rr_nodes = rr_graph.num_rr_nodes; num_rr_nodes = rr_graph.num_rr_nodes;
rr_node = rr_graph.rr_node; rr_node = rr_graph.rr_node;
rr_node_indices = rr_graph.rr_node_indices; rr_node_indices = rr_graph.rr_node_indices;
rr_graph_externals(timing_inf, segment_inf, num_seg_types, chan_width, rr_graph_externals(timing_inf, segment_inf, num_seg_types, chan_width,
wire_to_ipin_switch, base_cost_type); wire_to_ipin_switch, base_cost_type);

8
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp
View File

@ -354,7 +354,7 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph,
t_track2track_map* track2track_map) { t_track2track_map* track2track_map) {
for (size_t side = 0; side < from_tracks.size(); ++side) { for (size_t side = 0; side < from_tracks.size(); ++side) {
Side side_manager(side); Side side_manager(side);
enum e_side gsb_side = side_manager.get_side(); enum e_side from_side = side_manager.get_side();
/* Find the other sides where the start tracks will locate */ /* Find the other sides where the start tracks will locate */
std::vector<enum e_side> to_track_sides; std::vector<enum e_side> to_track_sides;
/* 0. opposite side */ /* 0. opposite side */
@ -375,9 +375,13 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph,
if (0 == to_tracks[to_side_index].size()) { if (0 == to_tracks[to_side_index].size()) {
continue; continue;
} }
/* Bypass those from_side is same as to_side */
if (from_side == to_side) {
continue;
}
/* Get other track_ids depending on the switch block pattern */ /* Get other track_ids depending on the switch block pattern */
/* Find the track ids that will start at the other sides */ /* Find the track ids that will start at the other sides */
std::vector<size_t> to_track_ids = get_switch_block_to_track_id(sb_type, Fs, gsb_side, inode, std::vector<size_t> to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode,
to_side, to_side,
to_tracks[to_side_index].size()); to_tracks[to_side_index].size());
/* Update the track2track_map: */ /* Update the track2track_map: */

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
View File

@ -1800,6 +1800,7 @@ void identify_rr_node_driver_switch(t_det_routing_arch RoutingArch,
} }
LL_rr_node[inode].driver_switch = LL_rr_node[inode].drive_switches[0]; LL_rr_node[inode].driver_switch = LL_rr_node[inode].drive_switches[0];
for (iedge = 0; iedge < LL_rr_node[inode].num_drive_rr_nodes; iedge++) { for (iedge = 0; iedge < LL_rr_node[inode].num_drive_rr_nodes; iedge++) {
if (LL_rr_node[inode].driver_switch != LL_rr_node[inode].drive_switches[iedge])
assert (LL_rr_node[inode].driver_switch == LL_rr_node[inode].drive_switches[iedge]); assert (LL_rr_node[inode].driver_switch == LL_rr_node[inode].drive_switches[iedge]);
} }
} }

11
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c
View File

@ -1340,11 +1340,12 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
if (TRUE == output_sb_xml) { if (TRUE == output_sb_xml) {
std::string fname_prefix(sb_xml_dir); std::string fname_prefix(sb_xml_dir);
/* Add slash if needed */ /* Add slash if needed */
if ('/' != fname_prefix.back()) { //if ('/' != fname_prefix.back()) {
fname_prefix += "/"; // fname_prefix += "/";
} //}
fname_prefix += "rotated_"; //fname_prefix += "rotated_";
write_rr_switch_block_to_xml(fname_prefix, rotated_rr_sb); //write_rr_switch_block_to_xml(fname_prefix, rotated_rr_sb);
write_rr_switch_block_to_xml(fname_prefix, rr_sb);
} }
} }
} }