Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
This commit is contained in:
Lalit Sharma
parent
57a4bccbac
commit
0cbad747a1
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@ -99,10 +99,6 @@ parser.add_argument('--arch_variable_file', type=str, default=None,
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# help="Key file for shell")
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parser.add_argument('--yosys_tmpl', type=str, default=None,
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help="Alternate yosys template, generates top_module.blif")
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parser.add_argument('--yosys_mode', type=str, default=None,
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help="Specify adder/no_adder mode for yosys run. Default is adder")
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parser.add_argument('--yosys_family', type=str, default="qlf_k4n8",
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help="Specify device family for yosys run")
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parser.add_argument('--disp', action="store_true",
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help="Open display while running VPR")
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parser.add_argument('--debug', action="store_true",
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@ -484,16 +480,6 @@ def run_yosys_with_abc():
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logger.exception("Failed to extract lut_size from XML file")
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clean_up_and_exit("")
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args.K = lut_size
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YS_MODE=""
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# Yosys valid mode option is "no_adder".
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if args.yosys_mode is not None:
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if args.yosys_mode.lower() == "no_adder":
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YS_MODE = "-" + args.yosys_mode
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else:
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logger.warning("Invalid value '" + args.yosys_mode + "' specified for synthesis_param 'bench_yosys_mode'")
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logger.warning("Considering default yosys mode i.e. adder mode")
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# Yosys script parameter mapping
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ys_params = {
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"READ_VERILOG_FILE": " \n".join([
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@ -502,9 +488,22 @@ def run_yosys_with_abc():
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"TOP_MODULE": args.top_module,
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"LUT_SIZE": lut_size,
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"OUTPUT_BLIF": args.top_module+"_yosys_out.blif",
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"YOSYS_FAMILY": args.yosys_family,
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"YOSYS_MODE": YS_MODE,
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}
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for indx in range(0, len(OpenFPGAArgs), 2):
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tmpVar = OpenFPGAArgs[indx][2:].upper()
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ys_params[tmpVar] = OpenFPGAArgs[indx+1]
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if 'YOSYS_FAMILY' not in ys_params.keys():
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# define default family as 'qlf_k4n8'
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ys_params['YOSYS_FAMILY'] = "qlf_k4n8"
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# prefix value of YOSYS_MODE with '-' as an option in yosys script
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if 'YOSYS_MODE' in ys_params.keys():
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ys_params['YOSYS_MODE'] = "-" + ys_params['YOSYS_MODE']
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else:
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ys_params['YOSYS_MODE'] = ""
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yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join(
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cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys")
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tmpl = Template(open(yosys_template, encoding='utf-8').read())
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@ -255,8 +255,6 @@ def generate_each_task_actions(taskname):
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# Read provided benchmark configurations
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# Common configurations
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ys_for_task_common = SynthSection.get("bench_yosys_common")
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ys_yosys_mode = SynthSection.get("bench_yosys_mode")
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ys_yosys_family = SynthSection.get("bench_yosys_family")
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chan_width_common = SynthSection.get("bench_chan_width_common")
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# Individual benchmark configuration
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@ -265,10 +263,6 @@ def generate_each_task_actions(taskname):
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fallback="top")
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CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys",
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fallback=ys_for_task_common)
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CurrBenchPara["yosys_mode"] = SynthSection.get(bech_name+"_yosys_mode",
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fallback=ys_yosys_mode)
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CurrBenchPara["yosys_family"] = SynthSection.get(bech_name+"_yosys_family",
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fallback=ys_yosys_family)
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CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width",
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fallback=chan_width_common)
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@ -387,12 +381,6 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
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if benchmark_obj.get("ys_script"):
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command += ["--yosys_tmpl", benchmark_obj["ys_script"]]
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if benchmark_obj.get("yosys_mode"):
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command += ["--yosys_mode", benchmark_obj["yosys_mode"]]
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if benchmark_obj.get("yosys_family"):
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command += ["--yosys_family", benchmark_obj["yosys_family"]]
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if task_gc.getboolean("power_analysis"):
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command += ["--power"]
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command += ["--power_tech", task_gc.get("power_tech_file")]
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@ -21,6 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml
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openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml
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openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
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yosys_mode = no_adder
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
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@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_vpr_circuit_format=eblif
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yosys_mode = no_adder
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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@ -49,8 +50,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en
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[SYNTHESIS_PARAM]
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bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
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bench_yosys_mode=no_adder
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bench_yosys_family=qlf_k4n8
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bench0_top = io_tc1
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bench1_top = unsigned_mult_80
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bench2_top = bin2bcd
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