diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 3927459e9..bddda8d15 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -99,10 +99,6 @@ parser.add_argument('--arch_variable_file', type=str, default=None, # help="Key file for shell") parser.add_argument('--yosys_tmpl', type=str, default=None, help="Alternate yosys template, generates top_module.blif") -parser.add_argument('--yosys_mode', type=str, default=None, - help="Specify adder/no_adder mode for yosys run. Default is adder") -parser.add_argument('--yosys_family', type=str, default="qlf_k4n8", - help="Specify device family for yosys run") parser.add_argument('--disp', action="store_true", help="Open display while running VPR") parser.add_argument('--debug', action="store_true", @@ -484,16 +480,6 @@ def run_yosys_with_abc(): logger.exception("Failed to extract lut_size from XML file") clean_up_and_exit("") args.K = lut_size - - YS_MODE="" - # Yosys valid mode option is "no_adder". - if args.yosys_mode is not None: - if args.yosys_mode.lower() == "no_adder": - YS_MODE = "-" + args.yosys_mode - else: - logger.warning("Invalid value '" + args.yosys_mode + "' specified for synthesis_param 'bench_yosys_mode'") - logger.warning("Considering default yosys mode i.e. adder mode") - # Yosys script parameter mapping ys_params = { "READ_VERILOG_FILE": " \n".join([ @@ -502,9 +488,22 @@ def run_yosys_with_abc(): "TOP_MODULE": args.top_module, "LUT_SIZE": lut_size, "OUTPUT_BLIF": args.top_module+"_yosys_out.blif", - "YOSYS_FAMILY": args.yosys_family, - "YOSYS_MODE": YS_MODE, } + + for indx in range(0, len(OpenFPGAArgs), 2): + tmpVar = OpenFPGAArgs[indx][2:].upper() + ys_params[tmpVar] = OpenFPGAArgs[indx+1] + + if 'YOSYS_FAMILY' not in ys_params.keys(): + # define default family as 'qlf_k4n8' + ys_params['YOSYS_FAMILY'] = "qlf_k4n8" + + # prefix value of YOSYS_MODE with '-' as an option in yosys script + if 'YOSYS_MODE' in ys_params.keys(): + ys_params['YOSYS_MODE'] = "-" + ys_params['YOSYS_MODE'] + else: + ys_params['YOSYS_MODE'] = "" + yosys_template = args.yosys_tmpl if args.yosys_tmpl else os.path.join( cad_tools["misc_dir"], "ys_tmpl_yosys_vpr_flow.ys") tmpl = Template(open(yosys_template, encoding='utf-8').read()) diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 2d676c786..fa297932e 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -255,8 +255,6 @@ def generate_each_task_actions(taskname): # Read provided benchmark configurations # Common configurations ys_for_task_common = SynthSection.get("bench_yosys_common") - ys_yosys_mode = SynthSection.get("bench_yosys_mode") - ys_yosys_family = SynthSection.get("bench_yosys_family") chan_width_common = SynthSection.get("bench_chan_width_common") # Individual benchmark configuration @@ -265,10 +263,6 @@ def generate_each_task_actions(taskname): fallback="top") CurrBenchPara["ys_script"] = SynthSection.get(bech_name+"_yosys", fallback=ys_for_task_common) - CurrBenchPara["yosys_mode"] = SynthSection.get(bech_name+"_yosys_mode", - fallback=ys_yosys_mode) - CurrBenchPara["yosys_family"] = SynthSection.get(bech_name+"_yosys_family", - fallback=ys_yosys_family) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) @@ -387,12 +381,6 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf): if benchmark_obj.get("ys_script"): command += ["--yosys_tmpl", benchmark_obj["ys_script"]] - if benchmark_obj.get("yosys_mode"): - command += ["--yosys_mode", benchmark_obj["yosys_mode"]] - - if benchmark_obj.get("yosys_family"): - command += ["--yosys_family", benchmark_obj["yosys_family"]] - if task_gc.getboolean("power_analysis"): command += ["--power"] command += ["--power_tech", task_gc.get("power_tech_file")] diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf index df236e1cf..3b68a8b83 100644 --- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf @@ -21,6 +21,7 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_8clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/repack_pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml +yosys_mode = no_adder [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf index 9724609d8..eba623ee8 100644 --- a/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_vpr_circuit_format=eblif +yosys_mode = no_adder [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -49,8 +50,7 @@ bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_en [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys -bench_yosys_mode=no_adder -bench_yosys_family=qlf_k4n8 + bench0_top = io_tc1 bench1_top = unsigned_mult_80 bench2_top = bin2bcd