[Regression] Upgraded runtime enviroment to python3.8
This commit is contained in:
Ganesh Gore
parent
0a29529731
commit
0b82b6439b
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@ -1,30 +1,6 @@
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abc
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ace2
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build
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cmake
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CMakeLists.txt
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deploy_key.enc
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docker
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Dockerfile
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docs
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libopenfpga
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libs
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LICENSE
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Makefile
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openfpga
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README.md
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run_local.bat
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run_local.sh
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vpr
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yosys
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# Ignore everything
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**
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!abc/abc
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!ace2/ace
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!openfpga/openfpga
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!vpr/vpr
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!yosys/yosys
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!yosys/yosys-abc
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!yosys/yosys-config
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!yosys/yosys-filterlib
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!yosys/yosys-smtbmc
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!yosys/share
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# Allow files and directories
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!/.github/**
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!/*.*
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@ -1,115 +1,116 @@
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#!/bin/bash
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set -e
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source openfpga.sh
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PYTHON_EXEC=python3.8
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###############################################
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "Basic regression tests";
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echo -e "Testing configuration chain of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
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echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
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run-task basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
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echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
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run-task basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
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run-task basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
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run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
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echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
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run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
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run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
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echo -e "Testing fixed device layout and routing channel width";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs
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run-task basic_tests/fixed_device_support --debug --show_thread_logs
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echo -e "Testing fabric Verilog generation only";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
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run-task basic_tests/generate_fabric --debug --show_thread_logs
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echo -e "Testing Verilog testbench generation only";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
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run-task basic_tests/generate_testbench --debug --show_thread_logs
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echo -e "Testing separated Verilog fabric netlists and testbench locations";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
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run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs
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echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
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run-task basic_tests/fixed_simulation_settings --debug --show_thread_logs
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echo -e "Testing Secured FPGA fabrics";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/generate_random_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs
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run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
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echo -e "Testing K4 series FPGA";
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echo -e "Testing K4N4 with facturable LUTs";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
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echo -e "Testing K4N4 with hard adders";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
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echo -e "Testing K4N4 without local routing architecture";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
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echo -e "Testing K4N4 with block RAM";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
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echo -e "Testing K4N4 with multiple lengths of routing segments";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
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echo -e "Testing K4N4 with 32-bit fracturable multiplier";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
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echo -e "Testing K4N5 with pattern based local routing";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
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run-task basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
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echo -e "Testing different tile organizations";
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echo -e "Testing tiles with pins only on top and left sides";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
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run-task basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs
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echo -e "Testing tiles with pins only on top and right sides";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
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run-task basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs
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echo -e "Testing tiles with pins only on bottom and right sides";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
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run-task basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs
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echo -e "Testing tiles with I/O in center grid";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/tileable_io --debug --show_thread_logs
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run-task basic_tests/tile_organization/tileable_io --debug --show_thread_logs
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echo -e "Testing global port definition from tiles";
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
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python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
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run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
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run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
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run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs
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echo -e "Testing yosys flow using custom ys script for running quicklogic device";
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python3 openfpga_flow/scripts/run_fpga_task.py quicklogic_tests/flow_test --debug --show_thread_logs
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run-task quicklogic_tests/flow_test --debug --show_thread_logs
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@ -6,7 +6,7 @@ on:
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push:
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pull_request:
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schedule:
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- cron: '0 0 * * 0 ' # weekly
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- cron: "0 0 * * 0 " # weekly
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# Environment variables
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env:
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@ -251,7 +251,7 @@ jobs:
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shell: bash
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run: |
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bash .github/workflows/install_dependencies_run.sh
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python3 -m pip install -r requirements.txt
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${PYTHON_EXEC} -m pip install -r requirements.txt
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rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. .
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source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh
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- name: Upload artifact
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@ -1,21 +1,22 @@
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#!/bin/bash
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set -e
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source openfpga.sh
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PYTHON_EXEC=python3.8
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###############################################
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "FPGA-Bitstream regression tests";
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echo -e "Testing bitstream generation for an auto-sized device";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
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run-task fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
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echo -e "Testing bitstream generation for an 48x48 FPGA device";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
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run-task fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
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echo -e "Testing bitstream generation for an 96x96 FPGA device";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
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run-task fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
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echo -e "Testing loading architecture bitstream from an external file";
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python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
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run-task fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
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@ -1,11 +1,12 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-SDC regression tests";
|
||||
|
||||
echo -e "Testing SDC generation with time units";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs
|
||||
run-task fpga_sdc/sdc_time_unit --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-SPICE regression tests";
|
||||
|
||||
echo -e "Testing FPGA-SPICE with netlist generation";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
|
||||
run-task fpga_spice/generate_spice --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -1,121 +1,121 @@
|
|||
#!/bin/bash
|
||||
|
||||
set -e
|
||||
|
||||
source openfpga.sh
|
||||
PYTHON_EXEC=python3.8
|
||||
###############################################
|
||||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "FPGA-Verilog Feature Tests";
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
|
||||
run-task fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
|
||||
run-task fpga_verilog/untileable --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with hard adder chain in CLBs ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
|
||||
run-task fpga_verilog/hard_adder --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with 16k block RAMs ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
|
||||
run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/reduced_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with embedded I/Os for an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/embedded_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with SoC I/Os for an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/soc_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with registerable I/Os for an FPGA ";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/registerable_io --debug --show_thread_logs
|
||||
run-task fpga_verilog/io/registerable_io --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with adder chain across an FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with shift register chain across an FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with scan chain across an FPGA";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
|
||||
run-task fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without buffers";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers with constant gnd input";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with routing multiplexers without constant inputs";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
||||
run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with behavioral description";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing implicit Verilog generation";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
|
||||
run-task fpga_verilog/implicit_verilog --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with flatten routing modules";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
|
||||
run-task fpga_verilog/flatten_routing --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with duplicated grid output pins";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
||||
run-task fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Verilog generation with spy output pads";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
|
||||
|
||||
run-task fpga_verilog/spypad --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Power-gating designs";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
||||
run-task fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
|
||||
|
||||
echo -e "Testing Depopulated crossbar in local routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/depopulate_crossbar --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing Fully connected output crossbar in local routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
||||
run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing through channels in tileable routing";
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
||||
python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
|
||||
run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
|
||||
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Please make sure you have ModelSim installed in the environment
|
||||
# Otherwise, it will fail
|
||||
#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
|
||||
#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
|
|
|
|||
|
|
@ -1,2 +1,4 @@
|
|||
apt-get update && apt-get install --no-install-recommends -y libdatetime-perl iverilog python3-pip git \
|
||||
libc6 libffi6 libgcc1 libreadline7 libstdc++6 libtcl8.6 python3 zlib1g libbz2-1.0 rsync
|
||||
apt-get install --no-install-recommends -y \
|
||||
libdatetime-perl libc6 libffi6 libgcc1 libreadline7 libstdc++6 \
|
||||
libtcl8.6 python3.8 python3-pip zlib1g libbz2-1.0 \
|
||||
iverilog git rsync make curl
|
||||
|
|
|
|||
|
|
@ -5,5 +5,10 @@ RUN apt-get update && apt-get install --no-install-recommends software-propertie
|
|||
RUN add-apt-repository ppa:git-core/ppa
|
||||
ADD .github/workflows/install_dependencies_run.sh install_dependencies_run.sh
|
||||
RUN bash install_dependencies_run.sh
|
||||
RUN curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py
|
||||
RUN python3.8 get-pip.py && rm get-pip.py
|
||||
RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.8 2
|
||||
RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 1
|
||||
ADD requirements.txt requirements.txt
|
||||
RUN python3 -m pip install -r requirements.txt
|
||||
ENV PYTHON_EXEC=python3.8
|
||||
RUN ${PYTHON_EXEC} -m pip install -r requirements.txt
|
||||
|
|
@ -409,7 +409,7 @@ def run_single_script(s, eachJob, job_list):
|
|||
with open(logfile, 'w+') as output:
|
||||
output.write("* "*20 + '\n')
|
||||
output.write("RunDirectory : %s\n" % os.getcwd())
|
||||
command = [gc["python_path"], gc["script_default"]] + \
|
||||
command = [os.getenv('PYTHON_EXEC', gc["python_path"]), gc["script_default"]] + \
|
||||
eachJob["commands"]
|
||||
output.write(" ".join(command) + '\n')
|
||||
output.write("* "*20 + '\n')
|
||||
|
|
|
|||
Loading…
Reference in New Issue