diff --git a/.dockerignore b/.dockerignore index becc94088..8801107ae 100644 --- a/.dockerignore +++ b/.dockerignore @@ -1,30 +1,6 @@ -abc -ace2 -build -cmake -CMakeLists.txt -deploy_key.enc -docker -Dockerfile -docs -libopenfpga -libs -LICENSE -Makefile -openfpga -README.md -run_local.bat -run_local.sh -vpr -yosys +# Ignore everything +** -!abc/abc -!ace2/ace -!openfpga/openfpga -!vpr/vpr -!yosys/yosys -!yosys/yosys-abc -!yosys/yosys-config -!yosys/yosys-filterlib -!yosys/yosys-smtbmc -!yosys/share +# Allow files and directories +!/.github/** +!/*.* \ No newline at end of file diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh index 875bbfd43..9d55c6e85 100755 --- a/.github/workflows/basic_reg_test.sh +++ b/.github/workflows/basic_reg_test.sh @@ -1,115 +1,116 @@ #!/bin/bash set -e - +source openfpga.sh +PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## echo -e "Basic regression tests"; echo -e "Testing configuration chain of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs +run-task basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs +run-task basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs +run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs +run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs +run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame --debug --show_thread_logs +run-task basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs +run-task basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs +run-task basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +run-task basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs +run-task basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs +run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs +run-task basic_tests/full_testbench/memory_bank --debug --show_thread_logs +run-task basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs +run-task basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs +run-task basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs +run-task basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs +run-task basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs +run-task basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs +run-task basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +run-task basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs +run-task basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs +run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs +run-task basic_tests/full_testbench/flatten_memory --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs echo -e "Testing fixed device layout and routing channel width"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs +run-task basic_tests/fixed_device_support --debug --show_thread_logs echo -e "Testing fabric Verilog generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs +run-task basic_tests/generate_fabric --debug --show_thread_logs echo -e "Testing Verilog testbench generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs +run-task basic_tests/generate_testbench --debug --show_thread_logs echo -e "Testing separated Verilog fabric netlists and testbench locations"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs +run-task basic_tests/custom_fabric_netlist_location --debug --show_thread_logs echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs +run-task basic_tests/fixed_simulation_settings --debug --show_thread_logs echo -e "Testing Secured FPGA fabrics"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs +run-task basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs +run-task basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs +run-task basic_tests/fabric_key/generate_random_key --debug --show_thread_logs +run-task basic_tests/fabric_key/load_external_key --debug --show_thread_logs +run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs +run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs echo -e "Testing K4 series FPGA"; echo -e "Testing K4N4 with facturable LUTs"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs +run-task basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs echo -e "Testing K4N4 with hard adders"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs +run-task basic_tests/k4_series/k4n4_adder --debug --show_thread_logs echo -e "Testing K4N4 without local routing architecture"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs +run-task basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs echo -e "Testing K4N4 with block RAM"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs +run-task basic_tests/k4_series/k4n4_bram --debug --show_thread_logs echo -e "Testing K4N4 with multiple lengths of routing segments"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs +run-task basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs echo -e "Testing K4N4 with 32-bit fracturable multiplier"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs +run-task basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs echo -e "Testing K4N5 with pattern based local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs +run-task basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs echo -e "Testing different tile organizations"; echo -e "Testing tiles with pins only on top and left sides"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs +run-task basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs echo -e "Testing tiles with pins only on top and right sides"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs +run-task basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs echo -e "Testing tiles with pins only on bottom and right sides"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs +run-task basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs echo -e "Testing tiles with I/O in center grid"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/tileable_io --debug --show_thread_logs +run-task basic_tests/tile_organization/tileable_io --debug --show_thread_logs echo -e "Testing global port definition from tiles"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs +run-task basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs +run-task basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs +run-task basic_tests/global_tile_ports/global_tile_4clock --debug --show_thread_logs echo -e "Testing yosys flow using custom ys script for running quicklogic device"; -python3 openfpga_flow/scripts/run_fpga_task.py quicklogic_tests/flow_test --debug --show_thread_logs +run-task quicklogic_tests/flow_test --debug --show_thread_logs diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index cda44639c..07552af47 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -6,7 +6,7 @@ on: push: pull_request: schedule: - - cron: '0 0 * * 0 ' # weekly + - cron: "0 0 * * 0 " # weekly # Environment variables env: @@ -48,27 +48,27 @@ jobs: fail-fast: false matrix: config: - - name: "Build Compatibility: GCC-5 (Ubuntu 18.04)" - cc: gcc-5 - cxx: g++-5 - - name: "Build Compatibility: GCC-6 (Ubuntu 18.04)" - cc: gcc-6 - cxx: g++-6 - - name: "Build Compatibility: GCC-7 (Ubuntu 18.04)" - cc: gcc-7 - cxx: g++-7 - - name: "Build Compatibility: GCC-8 (Ubuntu 18.04)" - cc: gcc-8 - cxx: g++-8 - - name: "Build Compatibility: GCC-9 (Ubuntu 18.04)" - cc: gcc-9 - cxx: g++-9 - - name: "Build Compatibility: Clang-6 (Ubuntu 18.04)" - cc: clang-6.0 - cxx: clang++-6.0 - - name: "Build Compatibility: Clang-8 (Ubuntu 18.04)" - cc: clang-8 - cxx: clang++-8 + - name: "Build Compatibility: GCC-5 (Ubuntu 18.04)" + cc: gcc-5 + cxx: g++-5 + - name: "Build Compatibility: GCC-6 (Ubuntu 18.04)" + cc: gcc-6 + cxx: g++-6 + - name: "Build Compatibility: GCC-7 (Ubuntu 18.04)" + cc: gcc-7 + cxx: g++-7 + - name: "Build Compatibility: GCC-8 (Ubuntu 18.04)" + cc: gcc-8 + cxx: g++-8 + - name: "Build Compatibility: GCC-9 (Ubuntu 18.04)" + cc: gcc-9 + cxx: g++-9 + - name: "Build Compatibility: Clang-6 (Ubuntu 18.04)" + cc: clang-6.0 + cxx: clang++-6.0 + - name: "Build Compatibility: Clang-8 (Ubuntu 18.04)" + cc: clang-8 + cxx: clang++-8 # Define the steps to run the build job env: CC: ${{ matrix.config.cc }} @@ -82,7 +82,7 @@ jobs: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 with: - submodules: true + submodules: true - name: Dump tool versions run: | @@ -251,7 +251,7 @@ jobs: shell: bash run: | bash .github/workflows/install_dependencies_run.sh - python3 -m pip install -r requirements.txt + ${PYTHON_EXEC} -m pip install -r requirements.txt rsync -am --exclude='openfpga_flow/**' /opt/openfpga/. . source openfpga.sh && source .github/workflows/${{matrix.config.name}}.sh - name: Upload artifact diff --git a/.github/workflows/fpga_bitstream_reg_test.sh b/.github/workflows/fpga_bitstream_reg_test.sh index ce3693555..06b507e94 100755 --- a/.github/workflows/fpga_bitstream_reg_test.sh +++ b/.github/workflows/fpga_bitstream_reg_test.sh @@ -1,21 +1,22 @@ #!/bin/bash set -e - +source openfpga.sh +PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## echo -e "FPGA-Bitstream regression tests"; echo -e "Testing bitstream generation for an auto-sized device"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs +run-task fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs echo -e "Testing bitstream generation for an 48x48 FPGA device"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs +run-task fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs echo -e "Testing bitstream generation for an 96x96 FPGA device"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs +run-task fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs echo -e "Testing loading architecture bitstream from an external file"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs +run-task fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs diff --git a/.github/workflows/fpga_sdc_reg_test.sh b/.github/workflows/fpga_sdc_reg_test.sh index 203106433..c4ff67a09 100755 --- a/.github/workflows/fpga_sdc_reg_test.sh +++ b/.github/workflows/fpga_sdc_reg_test.sh @@ -1,11 +1,12 @@ #!/bin/bash set -e - +source openfpga.sh +PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## echo -e "FPGA-SDC regression tests"; echo -e "Testing SDC generation with time units"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs +run-task fpga_sdc/sdc_time_unit --debug --show_thread_logs diff --git a/.github/workflows/fpga_spice_reg_test.sh b/.github/workflows/fpga_spice_reg_test.sh index defe17ec9..b58d75f8e 100755 --- a/.github/workflows/fpga_spice_reg_test.sh +++ b/.github/workflows/fpga_spice_reg_test.sh @@ -1,11 +1,12 @@ #!/bin/bash set -e - +source openfpga.sh +PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## echo -e "FPGA-SPICE regression tests"; echo -e "Testing FPGA-SPICE with netlist generation"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs +run-task fpga_spice/generate_spice --debug --show_thread_logs diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh index 4e01c1a0a..b7a47508e 100755 --- a/.github/workflows/fpga_verilog_reg_test.sh +++ b/.github/workflows/fpga_verilog_reg_test.sh @@ -1,121 +1,121 @@ #!/bin/bash set -e - +source openfpga.sh +PYTHON_EXEC=python3.8 ############################################### # OpenFPGA Shell with VPR8 ############################################## echo -e "FPGA-Verilog Feature Tests"; echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs +run-task fpga_verilog/lut_design/single_mode --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs +run-task fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: native fracturable LUT4 "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs +run-task fpga_verilog/lut_design/frac_native_lut4 --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs +run-task fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs +run-task fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs +run-task fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs echo -e "Testing Verilog generation with VPR's untileable routing architecture "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs +run-task fpga_verilog/untileable --debug --show_thread_logs echo -e "Testing Verilog generation with hard adder chain in CLBs "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs +run-task fpga_verilog/hard_adder --debug --show_thread_logs echo -e "Testing Verilog generation with 16k block RAMs "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs +run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs echo -e "Testing Verilog generation with 16k block RAMs spanning two columns "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs +run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs +run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs +run-task fpga_verilog/io/reduced_io --debug --show_thread_logs echo -e "Testing Verilog generation with embedded I/Os for an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs +run-task fpga_verilog/io/embedded_io --debug --show_thread_logs echo -e "Testing Verilog generation with SoC I/Os for an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs +run-task fpga_verilog/io/soc_io --debug --show_thread_logs echo -e "Testing Verilog generation with registerable I/Os for an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/registerable_io --debug --show_thread_logs +run-task fpga_verilog/io/registerable_io --debug --show_thread_logs echo -e "Testing Verilog generation with adder chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs +run-task fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs echo -e "Testing Verilog generation with shift register chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs +run-task fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs echo -e "Testing Verilog generation with scan chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs +run-task fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs +run-task fpga_verilog/mux_design/tree_structure --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs +run-task fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs +run-task fpga_verilog/mux_design/local_encoder --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers without buffers"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs +run-task fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers with input buffers only"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs +run-task fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers with output buffers only"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs +run-task fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs +run-task fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs echo -e "Testing Verilog generation with routing multiplexers without constant inputs"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs +run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs echo -e "Testing Verilog generation with behavioral description"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs +run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs echo -e "Testing implicit Verilog generation"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs +run-task fpga_verilog/implicit_verilog --debug --show_thread_logs echo -e "Testing Verilog generation with flatten routing modules"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs +run-task fpga_verilog/flatten_routing --debug --show_thread_logs echo -e "Testing Verilog generation with duplicated grid output pins"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs +run-task fpga_verilog/duplicated_grid_pin --debug --show_thread_logs echo -e "Testing Verilog generation with spy output pads"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs - +run-task fpga_verilog/spypad --debug --show_thread_logs echo -e "Testing Power-gating designs"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug +run-task fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug echo -e "Testing Depopulated crossbar in local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs +run-task fpga_verilog/depopulate_crossbar --debug --show_thread_logs echo -e "Testing Fully connected output crossbar in local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs +run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs echo -e "Testing through channels in tileable routing"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs +run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs +run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs -# Verify MCNC big20 benchmark suite with ModelSim +# Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 -#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim +#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 +#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim diff --git a/.github/workflows/install_dependencies_run.sh b/.github/workflows/install_dependencies_run.sh index 2654f648c..3efb3affb 100644 --- a/.github/workflows/install_dependencies_run.sh +++ b/.github/workflows/install_dependencies_run.sh @@ -1,2 +1,4 @@ -apt-get update && apt-get install --no-install-recommends -y libdatetime-perl iverilog python3-pip git \ - libc6 libffi6 libgcc1 libreadline7 libstdc++6 libtcl8.6 python3 zlib1g libbz2-1.0 rsync +apt-get install --no-install-recommends -y \ +libdatetime-perl libc6 libffi6 libgcc1 libreadline7 libstdc++6 \ +libtcl8.6 python3.8 python3-pip zlib1g libbz2-1.0 \ +iverilog git rsync make curl diff --git a/docker/Dockerfile.env b/docker/Dockerfile.env index b0221231f..699e153ea 100644 --- a/docker/Dockerfile.env +++ b/docker/Dockerfile.env @@ -5,5 +5,10 @@ RUN apt-get update && apt-get install --no-install-recommends software-propertie RUN add-apt-repository ppa:git-core/ppa ADD .github/workflows/install_dependencies_run.sh install_dependencies_run.sh RUN bash install_dependencies_run.sh +RUN curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py +RUN python3.8 get-pip.py && rm get-pip.py +RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.8 2 +RUN update-alternatives --install /usr/bin/python3 python3 /usr/bin/python3.6 1 ADD requirements.txt requirements.txt -RUN python3 -m pip install -r requirements.txt \ No newline at end of file +ENV PYTHON_EXEC=python3.8 +RUN ${PYTHON_EXEC} -m pip install -r requirements.txt \ No newline at end of file diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 7fb0346dc..9dbc5deaa 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -409,7 +409,7 @@ def run_single_script(s, eachJob, job_list): with open(logfile, 'w+') as output: output.write("* "*20 + '\n') output.write("RunDirectory : %s\n" % os.getcwd()) - command = [gc["python_path"], gc["script_default"]] + \ + command = [os.getenv('PYTHON_EXEC', gc["python_path"]), gc["script_default"]] + \ eachJob["commands"] output.write(" ".join(command) + '\n') output.write("* "*20 + '\n')