riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[engine] fixed bugs in subtiles. Revisited the usage of client functions

This commit is contained in:
tangxifan 2022-08-23 12:35:04 -07:00
parent 019e663e12
commit 0a6b794ef0
4 changed files with 17 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -762,10 +762,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
physical_tile_port.num_pins = 0; physical_tile_port.num_pins = 0;
/* Count the total number of pins for this type of sub tile */ /* Count the total number of pins for this type of sub tile */
int sub_tile_num_pins = 0; int sub_tile_num_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
for (const t_physical_tile_port& tile_port : sub_tile.ports) {
sub_tile_num_pins += tile_port.num_pins;
}
/* For each instance of the same sub tile type, find the port of the grid module according to the tile annotation /* For each instance of the same sub tile type, find the port of the grid module according to the tile annotation
* A tile may consist of multiple subtile, connect to all the pins from sub tiles */ * A tile may consist of multiple subtile, connect to all the pins from sub tiles */

5
openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
View File

@ -477,8 +477,9 @@ void print_analysis_sdc_disable_pb_block_unused_resources(std::fstream& fp,
VTR_ASSERT(false == physical_pb.empty()); VTR_ASSERT(false == physical_pb.empty());
} }
VTR_ASSERT(1 == grid_type->sub_tiles[grid_z].equivalent_sites.size()); int sub_tile_index = device_annotation.physical_tile_z_to_subtile_index(grid_type, grid_z);
t_pb_graph_node* pb_graph_head = grid_type->sub_tiles[grid_z].equivalent_sites[0]->pb_graph_head; VTR_ASSERT(1 == grid_type->sub_tiles[sub_tile_index].equivalent_sites.size());
t_pb_graph_node* pb_graph_head = grid_type->sub_tiles[sub_tile_index].equivalent_sites[0]->pb_graph_head;
VTR_ASSERT(nullptr != pb_graph_head); VTR_ASSERT(nullptr != pb_graph_head);
/* Find an unique name to the pb instance in this grid /* Find an unique name to the pb instance in this grid

22
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -97,15 +97,17 @@ std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_
} }
/* If the wanted port is invalid, it assumes that we want the full port */ /* If the wanted port is invalid, it assumes that we want the full port */
if (false == tile_port.is_valid()) { if (false == tile_port.is_valid()) {
for (int ipin = 0; ipin < physical_tile_port.num_pins; ++ipin) { for (int subtile_index = sub_tile.capacity.low; subtile_index <= sub_tile.capacity.high; subtile_index++) {
int pin_id = physical_tile_port.absolute_first_pin_index + ipin; for (int ipin = 0; ipin < physical_tile_port.num_pins; ++ipin) {
VTR_ASSERT(pin_id < physical_tile->num_pins); int pin_id = (subtile_index - sub_tile.capacity.low) * sub_tile.num_phy_pins / sub_tile.capacity.total() + physical_tile_port.absolute_first_pin_index + ipin;
/* Check if the pin is located on the wanted side */ VTR_ASSERT(pin_id < physical_tile->num_pins);
if (true == is_pin_locate_at_physical_tile_side(physical_tile, /* Check if the pin is located on the wanted side */
pin_width_offset, if (true == is_pin_locate_at_physical_tile_side(physical_tile,
pin_height_offset, pin_width_offset,
pin_id, pin_side)) { pin_height_offset,
pin_ids.push_back(pin_id); pin_id, pin_side)) {
pin_ids.push_back(pin_id);
}
} }
} }
continue; continue;
@ -122,7 +124,7 @@ std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_
exit(1); exit(1);
} }
for (const size_t& ipin : tile_port.pins()) { for (const size_t& ipin : tile_port.pins()) {
int pin_id = physical_tile_port.absolute_first_pin_index + ipin; int pin_id = physical_tile_port.absolute_first_pin_index + ipin * sub_tile.num_phy_pins / sub_tile.capacity.total() + ipin;
VTR_ASSERT(pin_id < physical_tile->num_pins); VTR_ASSERT(pin_id < physical_tile->num_pins);
/* Check if the pin is located on the wanted side */ /* Check if the pin is located on the wanted side */
if (true == is_pin_locate_at_physical_tile_side(physical_tile, if (true == is_pin_locate_at_physical_tile_side(physical_tile,

2
openfpga/src/utils/check_tile_annotation.cpp
View File

@ -125,7 +125,7 @@ int check_tile_annotation_conflicts_with_physical_tile(const TileAnnotation& til
continue; continue;
} }
BasicPort ref_tile_port(tile_port.name, tile_port.num_pins); BasicPort ref_tile_port(tile_port.name, sub_tile.capacity.total() * tile_port.num_pins);
/* Port size must be in range!!! */ /* Port size must be in range!!! */
if (false == ref_tile_port.contained(required_tile_port)) { if (false == ref_tile_port.contained(required_tile_port)) {
VTR_LOG_ERROR("Tile annotation port '%s[%lu:%lu]' is out of the range of physical tile port '%s[%lu:%lu]'!", VTR_LOG_ERROR("Tile annotation port '%s[%lu:%lu]' is out of the range of physical tile port '%s[%lu:%lu]'!",