diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp
index a9fcbc4e9..2f8133f57 100644
--- a/openfpga/src/fabric/build_top_module_connection.cpp
+++ b/openfpga/src/fabric/build_top_module_connection.cpp
@@ -762,10 +762,7 @@ int build_top_module_global_net_for_given_grid_module(ModuleManager& module_mana
     physical_tile_port.num_pins = 0;
 
     /* Count the total number of pins for this type of sub tile */
-    int sub_tile_num_pins = 0;
-    for (const t_physical_tile_port& tile_port : sub_tile.ports) { 
-      sub_tile_num_pins += tile_port.num_pins;
-    }
+    int sub_tile_num_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
 
     /* For each instance of the same sub tile type, find the port of the grid module according to the tile annotation
      * A tile may consist of multiple subtile, connect to all the pins from sub tiles */
diff --git a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
index ecbd79d0b..cffa6d4c6 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
@@ -477,8 +477,9 @@ void print_analysis_sdc_disable_pb_block_unused_resources(std::fstream& fp,
     VTR_ASSERT(false == physical_pb.empty());
   }
 
-  VTR_ASSERT(1 == grid_type->sub_tiles[grid_z].equivalent_sites.size());
-  t_pb_graph_node* pb_graph_head = grid_type->sub_tiles[grid_z].equivalent_sites[0]->pb_graph_head; 
+  int sub_tile_index = device_annotation.physical_tile_z_to_subtile_index(grid_type, grid_z);
+  VTR_ASSERT(1 == grid_type->sub_tiles[sub_tile_index].equivalent_sites.size());
+  t_pb_graph_node* pb_graph_head = grid_type->sub_tiles[sub_tile_index].equivalent_sites[0]->pb_graph_head; 
   VTR_ASSERT(nullptr != pb_graph_head);
 
   /* Find an unique name to the pb instance in this grid
diff --git a/openfpga/src/tile_direct/build_tile_direct.cpp b/openfpga/src/tile_direct/build_tile_direct.cpp
index 05a078664..0ae3ae432 100644
--- a/openfpga/src/tile_direct/build_tile_direct.cpp
+++ b/openfpga/src/tile_direct/build_tile_direct.cpp
@@ -97,15 +97,17 @@ std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_
       }
       /* If the wanted port is invalid, it assumes that we want the full port */
       if (false == tile_port.is_valid()) {
-        for (int ipin = 0; ipin < physical_tile_port.num_pins; ++ipin) {
-          int pin_id = physical_tile_port.absolute_first_pin_index + ipin;
-          VTR_ASSERT(pin_id < physical_tile->num_pins);
-          /* Check if the pin is located on the wanted side */
-          if (true == is_pin_locate_at_physical_tile_side(physical_tile,
-                                                          pin_width_offset,
-                                                          pin_height_offset,
-                                                          pin_id, pin_side)) {
-            pin_ids.push_back(pin_id);
+        for (int subtile_index = sub_tile.capacity.low; subtile_index <= sub_tile.capacity.high; subtile_index++) {
+          for (int ipin = 0; ipin < physical_tile_port.num_pins; ++ipin) {
+            int pin_id = (subtile_index - sub_tile.capacity.low) * sub_tile.num_phy_pins / sub_tile.capacity.total() + physical_tile_port.absolute_first_pin_index + ipin;
+            VTR_ASSERT(pin_id < physical_tile->num_pins);
+            /* Check if the pin is located on the wanted side */
+            if (true == is_pin_locate_at_physical_tile_side(physical_tile,
+                                                            pin_width_offset,
+                                                            pin_height_offset,
+                                                            pin_id, pin_side)) {
+              pin_ids.push_back(pin_id);
+            }
           }
         }
         continue;
@@ -122,7 +124,7 @@ std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_
         exit(1);
       }
       for (const size_t& ipin : tile_port.pins()) {
-        int pin_id = physical_tile_port.absolute_first_pin_index + ipin;
+        int pin_id = physical_tile_port.absolute_first_pin_index + ipin * sub_tile.num_phy_pins / sub_tile.capacity.total() + ipin;
         VTR_ASSERT(pin_id < physical_tile->num_pins);
         /* Check if the pin is located on the wanted side */
         if (true == is_pin_locate_at_physical_tile_side(physical_tile,
diff --git a/openfpga/src/utils/check_tile_annotation.cpp b/openfpga/src/utils/check_tile_annotation.cpp
index e5d732a03..4399fd888 100644
--- a/openfpga/src/utils/check_tile_annotation.cpp
+++ b/openfpga/src/utils/check_tile_annotation.cpp
@@ -125,7 +125,7 @@ int check_tile_annotation_conflicts_with_physical_tile(const TileAnnotation& til
               continue;
             }
 
-            BasicPort ref_tile_port(tile_port.name, tile_port.num_pins);
+            BasicPort ref_tile_port(tile_port.name, sub_tile.capacity.total() * tile_port.num_pins);
             /* Port size must be in range!!! */
             if (false == ref_tile_port.contained(required_tile_port)) {
               VTR_LOG_ERROR("Tile annotation port '%s[%lu:%lu]' is out of the range of physical tile port '%s[%lu:%lu]'!",