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[Doc] Update documentation about the new feature in pin constraint file

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tangxifan 2021-07-01 23:47:36 -06:00
parent 9074bffa68
commit 0851075bc9
1 changed files with 7 additions and 1 deletions
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8
docs/source/manual/file_formats/pin_constraints_file.rst
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@ -10,7 +10,7 @@ An example of design constraints is shown as follows.
.. code-block:: xml .. code-block:: xml
<pin_constraints> <pin_constraints>
<set_io pin="clk[0]" net="clk0"/> <set_io pin="clk[0]" net="clk0" default_value="1"/>
<set_io pin="clk[1]" net="clk1"/> <set_io pin="clk[1]" net="clk1"/>
<set_io pin="clk[2]" net="OPEN"/> <set_io pin="clk[2]" net="OPEN"/>
<set_io pin="clk[3]" net="OPEN"/> <set_io pin="clk[3]" net="OPEN"/>
@ -23,3 +23,9 @@ An example of design constraints is shown as follows.
.. option:: net="<string>" .. option:: net="<string>"
The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file. The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
.. option:: default_value="<string>"
The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli.
.. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration.