From 0851075bc96fe9bd4116bf7e65f89aeeb90ff372 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 1 Jul 2021 23:47:36 -0600
Subject: [PATCH] [Doc] Update documentation about the new feature in pin
 constraint file

---
 docs/source/manual/file_formats/pin_constraints_file.rst | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/docs/source/manual/file_formats/pin_constraints_file.rst b/docs/source/manual/file_formats/pin_constraints_file.rst
index c2a71c596..a172396f1 100644
--- a/docs/source/manual/file_formats/pin_constraints_file.rst
+++ b/docs/source/manual/file_formats/pin_constraints_file.rst
@@ -10,7 +10,7 @@ An example of design constraints is shown as follows.
 .. code-block:: xml
 
   <pin_constraints>
-    <set_io pin="clk[0]" net="clk0"/>
+    <set_io pin="clk[0]" net="clk0" default_value="1"/>
     <set_io pin="clk[1]" net="clk1"/>
     <set_io pin="clk[2]" net="OPEN"/>
     <set_io pin="clk[3]" net="OPEN"/>
@@ -23,3 +23,9 @@ An example of design constraints is shown as follows.
 .. option:: net="<string>"
 
   The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
+
+.. option:: default_value="<string>"
+
+  The default value of a net to be constrained. This is mainly used when generating testbenches. Valid value is ``0`` or ``1``. If defined as ``1``, the net is be driven by the inversion of its stimuli.
+
+  .. note:: This feature is mainly used to generate the correct stimuli for some pin whose polarity can be configurable. For example, the ``Reset`` pin of an FPGA fabric may be active-low or active-high depending on its configuration.