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Updated simulation example

This commit is contained in:
Ganesh Gore 2023-02-10 02:28:35 -07:00
parent a71d5d3606
commit 06a431c69e
3 changed files with 37 additions and 8 deletions
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17
openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf
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@ -15,23 +15,30 @@ verilog_output=true
timeout_each_job = 20*60
# fpga_flow= vpr_blif If input in in .blif format
# fpga_flow= yosys_vpr If input in in .v format
fpga_flow=vpr_blif
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:TASK_DIR}/example_script.openfpga
openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
[ARCHITECTURES]
arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml
[BENCHMARKS]
bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.blif
# bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.blif
bench1=${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
bench0_top = and2
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
bench0_act = ${PATH:TASK_DIR}/micro_benchmark/and2/and2.act
bench0_verilog = ${PATH:TASK_DIR}/micro_benchmark/and2/and2.v
bench1_top = mult8
bench1_verilog = ${PATH:TASK_DIR}/micro_benchmark/mult8/mult8.v
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=

6
openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga
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@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@ -55,9 +55,9 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend
# - Turn on every options here

22
openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/mult8/mult8.v Normal file
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@ -0,0 +1,22 @@
//-------------------------------------------------------
// Functionality: A 8-bit combinational multiply circuit
//-------------------------------------------------------
module mult8(a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7,
b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7,
out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7,
out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15);
input a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7;
input b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7;
output out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7;
output out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15;
assign a = {a_0, a_1, a_2, a_3, a_4, a_5, a_6, a_7};
assign b = {b_0, b_1, b_2, b_3, b_4, b_5, b_6, b_7};
assign out = {out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7, out_8, out_9, out_10, out_11, out_12, out_13, out_14, out_15};
assign out = a*b;
endmodule