[Yosys] Corrected output filename in QLyosys

2020-12-16 10:40:06 -07:00 · 2020-12-16 10:40:06 -07:00 · 061c6ce16d
parent 913d562126
commit 061c6ce16d
1 changed files with 1 additions and 2 deletions
--- a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
+++ b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
@ -2,5 +2,4 @@
 # Read verilog files
 ${READ_VERILOG_FILE}

-synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -openfpga -top ${TOP_MODULE}
-
+synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE}