From 061c6ce16db6de5c6b413b884db022511118fba2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 16 Dec 2020 10:40:06 -0700 Subject: [PATCH] [Yosys] Corrected output filename in QLyosys --- openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys index ce527daa0..8d2e426fe 100644 --- a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys +++ b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys @@ -2,5 +2,4 @@ # Read verilog files ${READ_VERILOG_FILE} -synth_quicklogic -blif ${TOP_MODULE}.eblif -family ap3 -vpr -openfpga -top ${TOP_MODULE} - +synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE} \ No newline at end of file