fixed CI errors
This commit is contained in:
Andrew Pond
parent
29f67479cc
commit
05c4a253cc
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@ -1,6 +1,6 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --sort_gsb_chan_node_in_edges
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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@ -72,3 +72,4 @@ exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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{"mode":"full","isActive":false}
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@ -0,0 +1,75 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION}
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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{"mode":"full","isActive":false}
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@ -0,0 +1,48 @@
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// Basic DFF
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module \$_DFF_P_ (D, C, Q);
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input D;
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input C;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
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endmodule
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// Async active-high reset
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module \$_DFF_PP0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
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endmodule
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// Async active-high set
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module \$_DFF_PP1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
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endmodule
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// Async active-low reset
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module \$_DFF_PN0_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
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endmodule
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// Async active-low set
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module \$_DFF_PN1_ (D, C, R, Q);
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input D;
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input C;
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input R;
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output Q;
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parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
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dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
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endmodule
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@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=3x2
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# Yosys script parameters
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yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
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yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt
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yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v
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yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
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yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt
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yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
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@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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# Yosys script parameters
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yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
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yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
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yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v
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yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
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@ -519,12 +519,12 @@
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<input name="cin" num_pins="1"/>
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<output name="cout" num_pins="1"/>
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<output name="sumout" num_pins="1"/>
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<delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
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<delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
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@ -754,12 +754,12 @@
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<input name="cin" num_pins="1"/>
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<output name="cout" num_pins="1"/>
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<output name="sumout" num_pins="1"/>
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<delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
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<delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
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</pb_type>
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<!-- Define multi-mode flip-flop -->
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<pb_type name="ff" num_pb="1">
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