diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
index 5c155b5b9..c8f8105fb 100644
--- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
 # to debug use --verbose options
-link_openfpga_arch --sort_gsb_chan_node_in_edges
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@@ -72,3 +72,4 @@ exit
 
 # Note :
 # To run verification at the end of the flow maintain source in ./SRC directory
+{"mode":"full","isActive":false}
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga
new file mode 100644
index 000000000..506364e30
--- /dev/null
+++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga
@@ -0,0 +1,75 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION}
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
+{"mode":"full","isActive":false}
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v
new file mode 100644
index 000000000..f8eed8db0
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v
@@ -0,0 +1,48 @@
+// Basic DFF
+module \$_DFF_P_ (D, C, Q);
+    input D;
+    input C;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
+endmodule
+
+// Async active-high reset
+module \$_DFF_PP0_ (D, C, R, Q);
+    input D;
+    input C;
+    input R;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
+endmodule
+
+// Async active-high set
+module \$_DFF_PP1_ (D, C, R, Q);
+    input D;
+    input C;
+    input R;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
+endmodule
+
+// Async active-low reset
+module \$_DFF_PN0_ (D, C, R, Q);
+    input D;
+    input C;
+    input R;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
+endmodule
+
+// Async active-low set
+module \$_DFF_PN1_ (D, C, R, Q);
+    input D;
+    input C;
+    input R;
+    output Q;
+    parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+    dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
+endmodule
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf
index 6caa13456..91c1237fc 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf
@@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_vpr_device_layout=3x2
 # Yosys script parameters
-yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
-yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt
-yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v
+yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
+yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt
+yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
index 2408323ed..bdbb241e7 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
@@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
 # Yosys script parameters
-yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
-yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
+yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v
+yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
index a967f67a3..2ff83dc49 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
@@ -519,12 +519,12 @@
               <input name="cin" num_pins="1"/>
               <output name="cout" num_pins="1"/>
               <output name="sumout" num_pins="1"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
             </pb_type>
             <interconnect>
               <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
@@ -754,12 +754,12 @@
               <input name="cin" num_pins="1"/>
               <output name="cout" num_pins="1"/>
               <output name="sumout" num_pins="1"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="${ADDER_LUT4_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2OUT_DELAY}" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_CIN2OUT_DELAY}" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_IN2COUT_DELAY}" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="${ADDER_CIN2COUT_DELAY}" in_port="adder.cin" out_port="adder.cout"/>
             </pb_type>
             <!-- Define multi-mode flip-flop -->
             <pb_type name="ff" num_pb="1">