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use typedef to short the module pin information

This commit is contained in:
tangxifan 2020-06-30 18:07:22 -06:00
parent 2e7684b746
commit 05187f8aa4
4 changed files with 90 additions and 88 deletions
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20
openfpga/src/fabric/build_routing_module_utils.cpp
View File

@ -21,7 +21,7 @@ namespace openfpga {
* Find the port id and pin id for a routing track in the switch
* block module with a given rr_node
********************************************************************/
std::pair<ModulePortId, size_t> find_switch_block_module_chan_port(const ModuleManager& module_manager,
ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
@ -40,7 +40,7 @@ std::pair<ModulePortId, size_t> find_switch_block_module_chan_port(const ModuleM
/* Must find a valid port id in the Switch Block module */
ModulePortId chan_port_id = module_manager.find_module_port(sb_module, chan_port_name);
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, chan_port_id));
return std::pair<ModulePortId, size_t>(chan_port_id, index / 2);
return ModulePinInfo(chan_port_id, index / 2);
}
/*********************************************************************
@ -62,14 +62,14 @@ std::pair<ModulePortId, size_t> find_switch_block_module_chan_port(const ModuleM
* 2. When the input is a routing track, the input_side should be
* the side of the node locating on the switch block
********************************************************************/
std::pair<ModulePortId, size_t> find_switch_block_module_input_port(const ModuleManager& module_manager,
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
const RRNodeId& input_rr_node) {
/* Deposit an invalid value */
std::pair<ModulePortId, size_t> input_port(ModulePortId::INVALID(), 0);
ModulePinInfo input_port(ModulePortId::INVALID(), 0);
/* Generate the input port object */
switch (rr_graph.node_type(input_rr_node)) {
/* case SOURCE: */
@ -107,12 +107,12 @@ std::pair<ModulePortId, size_t> find_switch_block_module_input_port(const Module
/*********************************************************************
* Generate a list of input ports for routing multiplexer inside the switch block
********************************************************************/
std::vector<std::pair<ModulePortId, size_t>> find_switch_block_module_input_ports(const ModuleManager& module_manager,
std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes) {
std::vector<std::pair<ModulePortId, size_t>> input_ports;
std::vector<ModulePinInfo> input_ports;
for (const RRNodeId& input_rr_node : input_rr_nodes) {
/* Find the side where the input locates in the Switch Block */
@ -133,13 +133,13 @@ std::vector<std::pair<ModulePortId, size_t>> find_switch_block_module_input_port
* Generate an input port for routing multiplexer inside the connection block
* which is the middle output of a routing track
********************************************************************/
std::pair<ModulePortId, size_t> find_connection_block_module_chan_port(const ModuleManager& module_manager,
ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& chan_rr_node) {
std::pair<ModulePortId, size_t> input_port_info;
ModulePinInfo input_port_info;
/* Generate the input port object */
switch (rr_graph.node_type(chan_rr_node)) {
case CHANX:
@ -195,13 +195,13 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
* Generate a list of routing track middle output ports
* for routing multiplexer inside the connection block
********************************************************************/
std::vector<std::pair<ModulePortId, size_t>> find_connection_block_module_input_ports(const ModuleManager& module_manager,
std::vector<ModulePinInfo> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const std::vector<RRNodeId>& input_rr_nodes) {
std::vector<std::pair<ModulePortId, size_t>> input_ports;
std::vector<ModulePinInfo> input_ports;
for (auto input_rr_node : input_rr_nodes) {
input_ports.push_back(find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, input_rr_node));

12
openfpga/src/fabric/build_routing_module_utils.h
View File

@ -18,7 +18,9 @@
/* begin namespace openfpga */
namespace openfpga {
std::pair<ModulePortId, size_t> find_switch_block_module_chan_port(const ModuleManager& module_manager,
typedef std::pair<ModulePortId, size_t> ModulePinInfo;
ModulePinInfo find_switch_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
@ -26,20 +28,20 @@ std::pair<ModulePortId, size_t> find_switch_block_module_chan_port(const ModuleM
const RRNodeId& cur_rr_node,
const PORTS& cur_rr_node_direction);
std::pair<ModulePortId, size_t> find_switch_block_module_input_port(const ModuleManager& module_manager,
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const e_side& input_side,
const RRNodeId& input_rr_node);
std::vector<std::pair<ModulePortId, size_t>> find_switch_block_module_input_ports(const ModuleManager& module_manager,
std::vector<ModulePinInfo> find_switch_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& sb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
const std::vector<RRNodeId>& input_rr_nodes);
std::pair<ModulePortId, size_t> find_connection_block_module_chan_port(const ModuleManager& module_manager,
ModulePinInfo find_connection_block_module_chan_port(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,
@ -52,7 +54,7 @@ ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_
const RRGSB& rr_gsb,
const RRNodeId& src_rr_node);
std::vector<std::pair<ModulePortId, size_t>> find_connection_block_module_input_ports(const ModuleManager& module_manager,
std::vector<ModulePinInfo> find_connection_block_module_input_ports(const ModuleManager& module_manager,
const ModuleId& cb_module,
const RRGraph& rr_graph,
const RRGSB& rr_gsb,

22
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -49,7 +49,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
const RRNodeId& drive_rr_node,
const std::map<ModulePortId, std::vector<ModuleNetId>>& input_port_to_module_nets) {
/* Find the name of output port */
std::pair<ModulePortId, size_t> output_port_info = find_switch_block_module_chan_port(module_manager, sb_module,
ModulePinInfo output_port_info = find_switch_block_module_chan_port(module_manager, sb_module,
rr_graph, rr_gsb,
chan_side, cur_rr_node, OUT_PORT);
enum e_side input_pin_side = chan_side;
@ -81,7 +81,7 @@ void build_switch_block_module_short_interc(ModuleManager& module_manager,
exit(1);
}
/* Find the name of input port */
std::pair<ModulePortId, size_t> input_port_info = find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
ModulePinInfo input_port_info = find_switch_block_module_input_port(module_manager, sb_module, rr_graph, rr_gsb, input_pin_side, drive_rr_node);
/* The input port and output port must match in size */
BasicPort input_port = module_manager.module_port(sb_module, input_port_info.first);
@ -137,7 +137,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
module_manager.set_child_instance_name(sb_module, mux_module, mux_instance_id, mux_instance_name);
/* Generate input ports that are wired to the input bus of the routing multiplexer */
std::vector<std::pair<ModulePortId, size_t>> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_graph, rr_gsb, driver_rr_nodes);
std::vector<ModulePinInfo> sb_input_port_ids = find_switch_block_module_input_ports(module_manager, sb_module, rr_graph, rr_gsb, driver_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
@ -167,7 +167,7 @@ void build_switch_block_mux_module(ModuleManager& module_manager,
ModulePortId mux_output_port_id = module_manager.find_module_port(mux_module, circuit_lib.port_prefix(mux_model_output_ports[0]));
VTR_ASSERT(true == module_manager.valid_module_port_id(mux_module, mux_output_port_id));
BasicPort mux_output_port = module_manager.module_port(mux_module, mux_output_port_id);
std::pair<ModulePortId, size_t> sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_graph, rr_gsb, chan_side, cur_rr_node, OUT_PORT);
ModulePinInfo sb_output_port_id = find_switch_block_module_chan_port(module_manager, sb_module, rr_graph, rr_gsb, chan_side, cur_rr_node, OUT_PORT);
BasicPort sb_output_port = module_manager.module_port(sb_module, sb_output_port_id.first);
/* Check port size should match */
@ -471,7 +471,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
const RRNodeId& src_rr_node,
const std::map<std::pair<ModulePortId, size_t>, ModuleNetId>& input_port_to_module_nets) {
const std::map<ModulePinInfo, ModuleNetId>& input_port_to_module_nets) {
/* Ensure we have only one 1 driver node */
std::vector<RRNodeId> driver_rr_nodes = get_rr_graph_configurable_driver_nodes(rr_graph, src_rr_node);
@ -502,7 +502,7 @@ void build_connection_block_module_short_interc(ModuleManager& module_manager,
VTR_ASSERT((CHANX == rr_graph.node_type(driver_rr_node)) || (CHANY == rr_graph.node_type(driver_rr_node)));
/* Create port description for the routing track middle output */
std::pair<ModulePortId, size_t> input_port_info = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
ModulePinInfo input_port_info = find_connection_block_module_chan_port(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_node);
/* Create port description for input pin of a CLB */
ModulePortId ipin_port_id = find_connection_block_module_ipin_port(module_manager, cb_module, rr_graph, rr_gsb, src_rr_node);
@ -533,7 +533,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_side& cb_ipin_side,
const size_t& ipin_index,
const std::map<std::pair<ModulePortId, size_t>, ModuleNetId>& input_port_to_module_nets) {
const std::map<ModulePinInfo, ModuleNetId>& input_port_to_module_nets) {
const RRNodeId& cur_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
/* Check current rr_node is an input pin of a CLB */
VTR_ASSERT(IPIN == rr_graph.node_type(cur_rr_node));
@ -566,7 +566,7 @@ void build_connection_block_mux_module(ModuleManager& module_manager,
module_manager.set_child_instance_name(cb_module, mux_module, mux_instance_id, mux_instance_name);
/* TODO: Generate input ports that are wired to the input bus of the routing multiplexer */
std::vector<std::pair<ModulePortId, size_t>> cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
std::vector<ModulePinInfo> cb_input_port_ids = find_connection_block_module_input_ports(module_manager, cb_module, rr_graph, rr_gsb, cb_type, driver_rr_nodes);
/* Link input bus port to Switch Block inputs */
std::vector<CircuitPortId> mux_model_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
@ -646,7 +646,7 @@ void build_connection_block_interc_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const e_side& cb_ipin_side,
const size_t& ipin_index,
const std::map<std::pair<ModulePortId, size_t>, ModuleNetId>& input_port_to_module_nets) {
const std::map<ModulePinInfo, ModuleNetId>& input_port_to_module_nets) {
const RRNodeId& src_rr_node = rr_gsb.get_ipin_node(cb_ipin_side, ipin_index);
if (1 > rr_graph.node_in_edges(src_rr_node).size()) {
@ -770,7 +770,7 @@ void build_connection_block_module(ModuleManager& module_manager,
}
/* Create a cache (fast look up) for module nets whose source are input ports */
std::map<std::pair<ModulePortId, size_t>, ModuleNetId> input_port_to_module_nets;
std::map<ModulePinInfo, ModuleNetId> input_port_to_module_nets;
/* Generate short-wire connection for each routing track :
* Each input port is short-wired to its output port
@ -783,7 +783,7 @@ void build_connection_block_module(ModuleManager& module_manager,
ModuleNetId net = create_module_source_pin_net(module_manager, cb_module, cb_module, 0, chan_input_port_id, chan_input_port.pins()[pin_id]);
module_manager.add_module_net_sink(cb_module, net, cb_module, 0, chan_output_port_id, chan_output_port.pins()[pin_id]);
/* Cache the module net */
input_port_to_module_nets[std::pair<ModulePortId, size_t>(chan_input_port_id, chan_input_port.pins()[pin_id])] = net;
input_port_to_module_nets[ModulePinInfo(chan_input_port_id, chan_input_port.pins()[pin_id])] = net;
}
/* Add sub modules of routing multiplexers or direct interconnect*/

14
openfpga/src/fpga_sdc/pnr_sdc_routing_writer.cpp
View File

@ -67,7 +67,7 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
|| ( CHANY == rr_graph.node_type(output_rr_node) ));
/* Find the module port corresponding to the output rr_node */
std::pair<ModulePortId, size_t> module_output_port = find_switch_block_module_chan_port(module_manager,
ModulePinInfo module_output_port = find_switch_block_module_chan_port(module_manager,
sb_module,
rr_graph,
rr_gsb,
@ -76,14 +76,14 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
OUT_PORT);
/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
std::vector<std::pair<ModulePortId, size_t>> module_input_ports = find_switch_block_module_input_ports(module_manager,
std::vector<ModulePinInfo> module_input_ports = find_switch_block_module_input_ports(module_manager,
sb_module,
rr_graph,
rr_gsb,
get_rr_graph_configurable_driver_nodes(rr_graph, output_rr_node));
/* Find timing constraints for each path (edge) */
std::map<std::pair<ModulePortId, size_t>, float> switch_delays;
std::map<ModulePinInfo, float> switch_delays;
size_t edge_counter = 0;
for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
/* Get the switch delay */
@ -93,7 +93,7 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
}
/* Find the starting points */
for (const std::pair<ModulePortId, size_t>& module_input_port : module_input_ports) {
for (const ModulePinInfo& module_input_port : module_input_ports) {
/* If we have a zero-delay path to contrain, we will skip unless users want so */
if ( (false == constrain_zero_delay_paths)
&& (0. == switch_delays[module_input_port]) ) {
@ -343,7 +343,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
output_rr_node);
/* Find the module port corresponding to the fan-in rr_nodes of the output rr_node */
std::vector<std::pair<ModulePortId, size_t>> module_input_ports = find_connection_block_module_input_ports(module_manager,
std::vector<ModulePinInfo> module_input_ports = find_connection_block_module_input_ports(module_manager,
cb_module,
rr_graph,
rr_gsb,
@ -351,7 +351,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
input_rr_nodes);
/* Find timing constraints for each path (edge) */
std::map<std::pair<ModulePortId, size_t>, float> switch_delays;
std::map<ModulePinInfo, float> switch_delays;
size_t edge_counter = 0;
for (const RREdgeId& edge : rr_graph.node_configurable_in_edges(output_rr_node)) {
/* Get the switch delay */
@ -361,7 +361,7 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
}
/* Find the starting points */
for (const std::pair<ModulePortId, size_t>& module_input_port : module_input_ports) {
for (const ModulePinInfo& module_input_port : module_input_ports) {
/* If we have a zero-delay path to contrain, we will skip unless users want so */
if ( (false == constrain_zero_delay_paths)
&& (0. == switch_delays[module_input_port]) ) {