Merge pull request #1810 from lnis-uofu/preloading_clean

Preloading clean

docs/source/manual/file_formats/index.rst

@@ -47,3 +47,5 @@ OpenFPGA widely uses XML format for interchangeable files
    fabric_hierarchy_file
 
    reference_file
+
+   unique_blocks

docs/source/manual/file_formats/unique_blocks.rst

@@ -0,0 +1,50 @@
+.. _file_formats_unique_blocks:
+
+Unique Blocks (.xml)
+--------------------
+
+A unique blocks file is formatted in XML. The unique blocks can be of type ``cbx``, ``cby``, or ``sb``. As illustrated by the XML code below, the file includes the type and coordinates of these unique blocks, as well as the coordinates of their corresponding instances.
+
+Configurable Block
+~~~~~~~~~~~~~~~~~~
+
+Unique blocks can be applied to various blocks, each of which can be of type ``cbx``, ``cby``, or ``sb``, and may have different coordinates.
+
+.. note::
+
+   For each block, a set of keys can be defined. For unique blocks, both keys and instances can be specified. However, if a unique block does not have an instance, only keys are permitted.
+
+   - ``type`` specifies the type of the unique block in the FPGA fabric. Valid values for ``type`` are ``cbx``, ``cby``, or ``sb``.
+   - ``x`` represents the x-coordinate of the unique block.
+   - ``y`` represents the y-coordinate of the unique block.
+
+Configurable Instance
+~~~~~~~~~~~~~~~~~~~~~
+
+A specific unique block can have multiple instances, where each instance is a mirrored version of the unique block. Each instance shares the same type as its parent block and includes information about its coordinates.
+
+.. note::
+
+   - ``x`` specifies the x-coordinate of the instance.
+   - ``y`` specifies the y-coordinate of the instance.
+
+The following content provides an example of a unique block file:
+
+.. code-block:: xml
+
+   <unique_blocks>
+       <block type="sb" x="0" y="0"/>
+       <block type="sb" x="0" y="1"/>
+       <block type="sb" x="1" y="0"/>
+       <block type="sb" x="1" y="1"/>
+       <block type="cbx" x="1" y="0">
+           <instance x="0" y="0"/>
+           <instance x="0" y="1"/>
+       </block>
+       <block type="cbx" x="1" y="1"/>
+       <block type="cby" x="0" y="1">
+           <instance x="0" y="0"/>
+           <instance x="1" y="0"/>
+       </block>
+       <block type="cby" x="1" y="1"/>
+   </unique_blocks>

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -548,3 +548,43 @@ report_reference
   .. option:: --verbose
 
     Show verbose info
+
+
+.. _openfpga_setup_commands_read_unique_blocks:
+
+read_unique_blocks
+~~~~~~~~~~~~~~~~~~~~
+
+  Read information of unique blocks from a given file.
+
+  .. option:: --file <string> 
+
+    Specify the file which contains unique block information. See details in :ref:`file_formats_unique_blocks`.
+
+  .. option:: --type <string>
+
+    Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML.
+  
+  .. option:: --verbose
+
+    Show verbose info
+
+.. _openfpga_setup_commands_write_unique_blocks:
+
+write_unique_blocks
+~~~~~~~~~~~~~~~~~~~~~
+
+  Write information of unique blocks from internal data structure to a given file.
+
+  .. option:: --file <string> 
+
+    Specify the file which we will write unique block information to. See details in :ref:`file_formats_unique_blocks`.
+
+  .. option:: --type <string>
+
+    Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML.
+  
+  .. option:: --verbose
+
+    Show verbose info
+

openfpga/src/annotation/device_rr_gsb.cpp

@@ -65,6 +65,8 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const {
       exit(1);
   }
 }
+/* Identify if unique blocks are preloaded or built */
+bool DeviceRRGSB::is_compressed() const { return is_compressed_; }
 
 /* Identify if a GSB actually exists at a location */
 bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph,
@@ -95,6 +97,88 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const {
   return sb_unique_module_.size();
 }
 
+/* get the coordinate of unique mirrors of switch blocks */
+vtr::Point<size_t> DeviceRRGSB::get_sb_unique_block_coord(size_t id) const {
+  return sb_unique_module_[id];
+}
+
+/* get the coordinates of the instances of a unique switch block */
+std::vector<vtr::Point<size_t>> DeviceRRGSB::get_sb_unique_block_instance_coord(
+  const vtr::Point<size_t>& unique_block_coord) const {
+  auto unique_module_id =
+    sb_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()];
+  std::vector<vtr::Point<size_t>> instance_map;
+  for (size_t location_x = 0; location_x < sb_unique_module_id_.size();
+       ++location_x) {
+    for (size_t location_y = 0; location_y < sb_unique_module_id_[0].size();
+         ++location_y) {
+      auto unique_module_id_instance =
+        sb_unique_module_id_[location_x][location_y];
+      if (unique_module_id_instance == unique_module_id) {
+        vtr::Point<size_t> instance_coord(location_x, location_y);
+        instance_map.push_back(instance_coord);
+      }
+    }
+  }
+  return instance_map;
+}
+
+/* get the coordinate of unique mirrors of connection blocks of CHANX type */
+vtr::Point<size_t> DeviceRRGSB::get_cbx_unique_block_coord(size_t id) const {
+  return cbx_unique_module_[id];
+}
+
+/* get the coordinates of the instances of a unique connection block of CHANX
+ * type */
+std::vector<vtr::Point<size_t>>
+DeviceRRGSB::get_cbx_unique_block_instance_coord(
+  const vtr::Point<size_t>& unique_block_coord) const {
+  auto unique_module_id =
+    cbx_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()];
+  std::vector<vtr::Point<size_t>> instance_map;
+  for (size_t location_x = 0; location_x < cbx_unique_module_id_.size();
+       ++location_x) {
+    for (size_t location_y = 0; location_y < cbx_unique_module_id_[0].size();
+         ++location_y) {
+      auto unique_module_id_instance =
+        cbx_unique_module_id_[location_x][location_y];
+      if (unique_module_id_instance == unique_module_id) {
+        vtr::Point<size_t> instance_coord(location_x, location_y);
+        instance_map.push_back(instance_coord);
+      }
+    }
+  }
+  return instance_map;
+}
+
+/* get the coordinate of unique mirrors of connection blocks of CHANY type */
+vtr::Point<size_t> DeviceRRGSB::get_cby_unique_block_coord(size_t id) const {
+  return cby_unique_module_[id];
+}
+
+/* get the coordinates of the instances of a unique connection block of CHANY
+ * type */
+std::vector<vtr::Point<size_t>>
+DeviceRRGSB::get_cby_unique_block_instance_coord(
+  const vtr::Point<size_t>& unique_block_coord) const {
+  auto unique_module_id =
+    cby_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()];
+  std::vector<vtr::Point<size_t>> instance_map;
+  for (size_t location_x = 0; location_x < cby_unique_module_id_.size();
+       ++location_x) {
+    for (size_t location_y = 0; location_y < cby_unique_module_id_[0].size();
+         ++location_y) {
+      auto unique_module_id_instance =
+        cby_unique_module_id_[location_x][location_y];
+      if (unique_module_id_instance == unique_module_id) {
+        vtr::Point<size_t> instance_coord(location_x, location_y);
+        instance_map.push_back(instance_coord);
+      }
+    }
+  }
+  return instance_map;
+}
+
 /* get the number of unique mirrors of switch blocks */
 size_t DeviceRRGSB::get_num_gsb_unique_module() const {
   return gsb_unique_module_.size();
@@ -172,6 +256,20 @@ void DeviceRRGSB::reserve(const vtr::Point<size_t>& coordinate) {
   }
 }
 
+void DeviceRRGSB::reserve_unique_modules() {
+  /* As rr_gsb_ has been built, it has valid size. Will reserve space for
+   * unique blocks according to rr_gsb_'s size*/
+  sb_unique_module_id_.resize(rr_gsb_.size());
+  cbx_unique_module_id_.resize(rr_gsb_.size());
+  cby_unique_module_id_.resize(rr_gsb_.size());
+
+  for (std::size_t i = 0; i < rr_gsb_.size(); ++i) {
+    sb_unique_module_id_[i].resize(rr_gsb_[i].size());
+    cbx_unique_module_id_[i].resize(rr_gsb_[i].size());
+    cby_unique_module_id_[i].resize(rr_gsb_[i].size());
+  }
+}
+
 /* Resize rr_switch_block array is needed*/
 void DeviceRRGSB::resize_upon_need(const vtr::Point<size_t>& coordinate) {
   if (coordinate.x() + 1 > rr_gsb_.size()) {
@@ -192,8 +290,8 @@ void DeviceRRGSB::resize_upon_need(const vtr::Point<size_t>& coordinate) {
   }
 }
 
-/* Add a switch block to the array, which will automatically identify and update
+/* Add a switch block to the array, which will automatically identify and
- * the lists of unique mirrors and rotatable mirrors */
+ * update the lists of unique mirrors and rotatable mirrors */
 void DeviceRRGSB::add_rr_gsb(const vtr::Point<size_t>& coordinate,
                              const RRGSB& rr_gsb) {
   /* Resize upon needs*/
@@ -215,8 +313,8 @@ RRGSB& DeviceRRGSB::get_mutable_gsb(const size_t& x, const size_t& y) {
   return get_mutable_gsb(coordinate);
 }
 
-/* Add a switch block to the array, which will automatically identify and update
+/* Add a switch block to the array, which will automatically identify and
- * the lists of unique mirrors and rotatable mirrors */
+ * update the lists of unique mirrors and rotatable mirrors */
 void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph,
                                          const t_rr_type& cb_type) {
   /* Make sure a clean start */
@@ -232,7 +330,8 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph,
         continue;
       }
 
-      /* Traverse the unique_mirror list and check it is an mirror of another */
+      /* Traverse the unique_mirror list and check it is an mirror of another
+       */
       for (size_t id = 0; id < get_num_cb_unique_module(cb_type); ++id) {
         const RRGSB& unique_module = get_cb_unique_module(cb_type, id);
         if (true == is_cb_mirror(rr_graph, device_annotation_, rr_gsb_[ix][iy],
@@ -255,8 +354,8 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph,
   }
 }
 
-/* Add a switch block to the array, which will automatically identify and update
+/* Add a switch block to the array, which will automatically identify and
- * the lists of unique mirrors and rotatable mirrors */
+ * update the lists of unique mirrors and rotatable mirrors */
 void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) {
   /* Make sure a clean start */
   clear_sb_unique_module();
@@ -267,7 +366,8 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) {
       bool is_unique_module = true;
       vtr::Point<size_t> sb_coordinate(ix, iy);
 
-      /* Traverse the unique_mirror list and check it is an mirror of another */
+      /* Traverse the unique_mirror list and check it is an mirror of another
+       */
       for (size_t id = 0; id < get_num_sb_unique_module(); ++id) {
         /* Check if the two modules have the same submodules,
          * if so, these two modules are the same, indicating the sb is not
@@ -294,8 +394,8 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) {
   }
 }
 
-/* Add a switch block to the array, which will automatically identify and update
+/* Add a switch block to the array, which will automatically identify and
- * the lists of unique mirrors and rotatable mirrors */
+ * update the lists of unique mirrors and rotatable mirrors */
 
 /* Find repeatable GSB block in the array */
 void DeviceRRGSB::build_gsb_unique_module() {
@@ -307,11 +407,12 @@ void DeviceRRGSB::build_gsb_unique_module() {
       bool is_unique_module = true;
       vtr::Point<size_t> gsb_coordinate(ix, iy);
 
-      /* Traverse the unique_mirror list and check it is an mirror of another */
+      /* Traverse the unique_mirror list and check it is an mirror of another
+       */
       for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) {
         /* We have alreay built sb and cb unique module list
-         * We just need to check if the unique module id of SBs, CBX and CBY are
+         * We just need to check if the unique module id of SBs, CBX and CBY
-         * the same or not
+         * are the same or not
          */
         const vtr::Point<size_t>& gsb_unique_module_coordinate =
           gsb_unique_module_[id];
@@ -339,6 +440,7 @@ void DeviceRRGSB::build_gsb_unique_module() {
       }
     }
   }
+  is_compressed_ = true;
 }
 
 void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) {
@@ -347,7 +449,8 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) {
   build_cb_unique_module(rr_graph, CHANX);
   build_cb_unique_module(rr_graph, CHANY);
 
-  build_gsb_unique_module();
+  build_gsb_unique_module(); /*is_compressed_ flip inside
+                                build_gsb_unique_module*/
 }
 
 void DeviceRRGSB::add_gsb_unique_module(const vtr::Point<size_t>& coordinate) {
@@ -408,6 +511,20 @@ void DeviceRRGSB::clear() {
 
   clear_sb_unique_module();
   clear_sb_unique_module_id();
+  is_compressed_ = false;
+}
+
+void DeviceRRGSB::clear_unique_modules() {
+  /* clean unique module lists */
+  clear_cb_unique_module(CHANX);
+  clear_cb_unique_module_id(CHANX);
+
+  clear_cb_unique_module(CHANY);
+  clear_cb_unique_module_id(CHANY);
+
+  clear_sb_unique_module();
+  clear_sb_unique_module_id();
+  is_compressed_ = false;
 }
 
 void DeviceRRGSB::clear_gsb() {
@@ -551,4 +668,82 @@ size_t DeviceRRGSB::get_cb_unique_module_index(
   return cb_unique_module_id;
 }
 
+/************************************************************************
+ * Preload unique blocks
+ ***********************************************************************/
+/* preload unique cbx blocks and their corresponding instance information. This
+ * function will be called when read_unique_blocks command invoked */
+void DeviceRRGSB::preload_unique_cbx_module(
+  const vtr::Point<size_t>& block_coordinate,
+  const std::vector<vtr::Point<size_t>>& instance_coords) {
+  /*check whether the preloaded value exceeds the limit */
+  size_t limit_x = cbx_unique_module_id_.size();
+  size_t limit_y = cbx_unique_module_id_[0].size();
+  VTR_ASSERT(block_coordinate.x() < limit_x);
+  VTR_ASSERT(block_coordinate.y() < limit_y);
+  add_cb_unique_module(CHANX, block_coordinate);
+  /* preload the unique block */
+  set_cb_unique_module_id(CHANX, block_coordinate,
+                          get_num_cb_unique_module(CHANX) - 1);
+
+  /* preload the instances of the unique block. Instance will have the same id
+   * as the unique block */
+  for (auto instance_location : instance_coords) {
+    VTR_ASSERT(instance_location.x() < limit_x);
+    VTR_ASSERT(instance_location.y() < limit_y);
+    set_cb_unique_module_id(
+      CHANX, instance_location,
+      cbx_unique_module_id_[block_coordinate.x()][block_coordinate.y()]);
+  }
+}
+
+/* preload unique cby blocks and their corresponding instance information. This
+ * function will be called when read_unique_blocks command invoked */
+void DeviceRRGSB::preload_unique_cby_module(
+  const vtr::Point<size_t>& block_coordinate,
+  const std::vector<vtr::Point<size_t>>& instance_coords) {
+  /*check whether the preloaded value exceeds the limit */
+  size_t limit_x = cby_unique_module_id_.size();
+  size_t limit_y = cby_unique_module_id_[0].size();
+
+  VTR_ASSERT(block_coordinate.x() < limit_x);
+  VTR_ASSERT(block_coordinate.y() < limit_y);
+  add_cb_unique_module(CHANY, block_coordinate);
+  /* preload the unique block */
+  set_cb_unique_module_id(CHANY, block_coordinate,
+                          get_num_cb_unique_module(CHANY) - 1);
+
+  /* preload the instances of the unique block. Instance will have the same id
+   * as the unique block */
+  for (auto instance_location : instance_coords) {
+    VTR_ASSERT(instance_location.x() < limit_x);
+    VTR_ASSERT(instance_location.y() < limit_y);
+    set_cb_unique_module_id(
+      CHANY, instance_location,
+      cby_unique_module_id_[block_coordinate.x()][block_coordinate.y()]);
+  }
+}
+
+/* preload unique sb blocks and their corresponding instance information. This
+ * function will be called when read_unique_blocks command invoked */
+void DeviceRRGSB::preload_unique_sb_module(
+  const vtr::Point<size_t>& block_coordinate,
+  const std::vector<vtr::Point<size_t>>& instance_coords) {
+  /*check whether the preloaded value exceeds the limit */
+  VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size());
+  VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size());
+  sb_unique_module_.push_back(block_coordinate);
+  /* Record the id of unique module */
+  sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()] =
+    sb_unique_module_.size() - 1;
+
+  /* each mirror instance of the unique module will have the same module id as
+   * the unique module */
+  for (auto instance_location : instance_coords) {
+    VTR_ASSERT(instance_location.x() < sb_unique_module_id_.size());
+    VTR_ASSERT(instance_location.y() < sb_unique_module_id_[0].size());
+    sb_unique_module_id_[instance_location.x()][instance_location.y()] =
+      sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()];
+  }
+}
 } /* End namespace openfpga*/

openfpga/src/annotation/device_rr_gsb.h

@@ -43,8 +43,28 @@ class DeviceRRGSB {
     const vtr::Point<size_t>& coordinate) const;
   size_t get_num_gsb_unique_module()
     const; /* get the number of unique mirrors of GSB */
+
   size_t get_num_sb_unique_module()
-    const; /* get the number of unique mirrors of switch blocks */
+    const; /* get the number of unique mirrors of SB */
+  vtr::Point<size_t> get_sb_unique_block_coord(
+    size_t id) const; /* get the coordinate of a unique switch block */
+  std::vector<vtr::Point<size_t>> get_sb_unique_block_instance_coord(
+    const vtr::Point<size_t>& unique_block_coord)
+    const; /* get the coordinates of the instances of a unique switch block */
+
+  vtr::Point<size_t> get_cbx_unique_block_coord(size_t id)
+    const; /* get the coordinate of a unique connection block of CHANX type */
+  std::vector<vtr::Point<size_t>> get_cbx_unique_block_instance_coord(
+    const vtr::Point<size_t>& unique_block_coord)
+    const; /* get the coordinates of the instances of a unique connection block
+              of CHANX type*/
+  vtr::Point<size_t> get_cby_unique_block_coord(size_t id)
+    const; /* get the coordinate of a unique connection block of CHANY type */
+  std::vector<vtr::Point<size_t>> get_cby_unique_block_instance_coord(
+    const vtr::Point<size_t>& unique_block_coord)
+    const; /* get the coordinates of the instances of a unique connection block
+              of CHANY type */
+
   const RRGSB& get_gsb_unique_module(
     const size_t& index) const; /* Get a rr-gsb which is a unique mirror */
   const RRGSB& get_sb_unique_module(const size_t& index)
@@ -69,13 +89,15 @@ class DeviceRRGSB {
                                     const vtr::Point<size_t>& coordinate) const;
 
  public: /* Mutators */
+  bool is_compressed() const;
+  void build_gsb_unique_module(); /* Add a switch block to the array, which will
+                                     automatically identify and update the lists
+                                     of unique mirrors and rotatable mirrors */
   void reserve(
     const vtr::Point<size_t>& coordinate); /* Pre-allocate the rr_switch_block
                                               array that the device requires */
-  void reserve_sb_unique_submodule_id(
+  void reserve_unique_modules(); /* Pre-allocate the rr_sb_unique_module_id
-    const vtr::Point<size_t>&
+                      matrix that the device requires */
-      coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the
-                      device requires */
   void resize_upon_need(
     const vtr::Point<size_t>&
       coordinate); /* Resize the rr_switch_block array if needed */
@@ -95,8 +117,27 @@ class DeviceRRGSB {
                                      automatically identify and update the lists
                                      of unique mirrors and rotatable mirrors */
   void clear();                   /* clean the content */
- private:                         /* Internal cleaners */
+  void preload_unique_cbx_module(
-  void clear_gsb();               /* clean the content */
+    const vtr::Point<size_t>& block_coordinate,
+    const std::vector<vtr::Point<size_t>>&
+      instance_coords); /* preload unique CBX blocks and their corresponding
+                           instance information. This function will be called
+                           when read_unique_blocks command invoked */
+  void preload_unique_cby_module(
+    const vtr::Point<size_t>& block_coordinate,
+    const std::vector<vtr::Point<size_t>>&
+      instance_coords); /* preload unique CBY blocks and their corresponding
+instance information. This function will be called
+when read_unique_blocks command invoked */
+  void preload_unique_sb_module(const vtr::Point<size_t>& block_coordinate,
+                                const std::vector<vtr::Point<size_t>>&
+                                  instance_coords); /* preload unique SB blocks
+                   and their corresponding instance information. This function
+                   will be called when read_unique_blocks command invoked */
+  void clear_unique_modules(); /* clean the content of unique blocks*/
+
+ private:                                                /* Internal cleaners */
+  void clear_gsb();                                      /* clean the content */
   void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */
   void clear_cb_unique_module_id(
     const t_rr_type& cb_type);       /* clean the content */
@@ -133,11 +174,11 @@ class DeviceRRGSB {
     const t_rr_type&
       cb_type); /* Add a switch block to the array, which will automatically
                    identify and update the lists of unique side module */
-  void build_gsb_unique_module(); /* Add a switch block to the array, which will
+
-                                     automatically identify and update the lists
+ private: /* Internal Data */
-                                     of unique mirrors and rotatable mirrors */
- private:                         /* Internal Data */
   std::vector<std::vector<RRGSB>> rr_gsb_;
+  bool is_compressed_ =
+    false; /* True if the unique blocks have been preloaded or built */
 
   std::vector<std::vector<size_t>>
     gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */

openfpga/src/annotation/read_xml_unique_blocks.cpp

@@ -0,0 +1,157 @@
+#include <string>
+/* Headers from pugi XML library */
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from libarchfpga */
+#include "arch_error.h"
+#include "command_exit_codes.h"
+#include "device_rr_gsb_utils.h"
+#include "openfpga_digest.h"
+#include "read_xml_unique_blocks.h"
+#include "read_xml_util.h"
+#include "rr_gsb.h"
+#include "write_xml_utils.h"
+
+/********************************************************************
+ * This file includes the top-level functions of this library
+ * which includes:
+ *  -- reads an XML file of unique blocks to the associated
+ * data structures: device_rr_gsb
+ *******************************************************************/
+namespace openfpga {
+/*read the instances' coordinate of a unique block from a xml file*/
+std::vector<vtr::Point<size_t>> read_xml_unique_instance_coords(
+  const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) {
+  std::vector<vtr::Point<size_t>> instance_coords;
+  for (pugi::xml_node xml_instance_info : xml_block_info.children()) {
+    if (xml_instance_info.name() == std::string("instance")) {
+      int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int();
+      int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int();
+      vtr::Point<size_t> instance_coordinate(instance_x, instance_y);
+      instance_coords.push_back(instance_coordinate);
+    }
+  }
+  return instance_coords;
+}
+
+/*read the unique block coordinate from a xml file */
+vtr::Point<size_t> read_xml_unique_block_coord(
+  const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) {
+  int block_x = get_attribute(xml_block_info, "x", loc_data).as_int();
+  int block_y = get_attribute(xml_block_info, "y", loc_data).as_int();
+  vtr::Point<size_t> block_coordinate(block_x, block_y);
+  return block_coordinate;
+}
+
+/*report information of read unique blocks*/
+void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb,
+                                      bool verbose_output) {
+  /* Report the stats */
+  VTR_LOGV(
+    verbose_output,
+    "Read %lu unique X-direction connection blocks from a total of %d "
+    "(compression rate=%.2f%)\n",
+    device_rr_gsb.get_num_cb_unique_module(CHANX),
+    find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX),
+    100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX) /
+              (float)device_rr_gsb.get_num_cb_unique_module(CHANX) -
+            1.));
+  VTR_LOGV(
+    verbose_output,
+    "Read %lu unique Y-direction connection blocks from a total of %d "
+    "(compression rate=%.2f%)\n",
+    device_rr_gsb.get_num_cb_unique_module(CHANY),
+    find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY),
+    100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY) /
+              (float)device_rr_gsb.get_num_cb_unique_module(CHANY) -
+            1.));
+
+  VTR_LOGV(verbose_output,
+           "Read %lu unique switch blocks from a total of %d (compression "
+           "rate=%.2f%)\n",
+           device_rr_gsb.get_num_sb_unique_module(),
+           find_device_rr_gsb_num_sb_modules(device_rr_gsb,
+                                             g_vpr_ctx.device().rr_graph),
+           100. * ((float)find_device_rr_gsb_num_sb_modules(
+                     device_rr_gsb, g_vpr_ctx.device().rr_graph) /
+                     (float)device_rr_gsb.get_num_sb_unique_module() -
+                   1.));
+
+  VTR_LOG(
+    "Read %lu unique general switch blocks from a total of %d "
+    "(compression "
+    "rate=%.2f%)\n",
+    device_rr_gsb.get_num_gsb_unique_module(),
+    find_device_rr_gsb_num_gsb_modules(device_rr_gsb,
+                                       g_vpr_ctx.device().rr_graph),
+    100. * ((float)find_device_rr_gsb_num_gsb_modules(
+              device_rr_gsb, g_vpr_ctx.device().rr_graph) /
+              (float)device_rr_gsb.get_num_gsb_unique_module() -
+            1.));
+}
+
+/*Parse XML codes about <unique_blocks> to an object of device_rr_gsb*/
+int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name,
+                           bool verbose_output) {
+  vtr::ScopedStartFinishTimer timer("Read unique blocks xml file");
+  /* Parse the file */
+  pugi::xml_document doc;
+  pugiutil::loc_data loc_data;
+  try {
+    loc_data = pugiutil::load_xml(doc, file_name);
+
+    pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data);
+    /* clear unique modules & reserve memory to relavant vectors */
+    device_rr_gsb.clear_unique_modules();
+    // vtr::Point<size_t> grid_coord(rr_gsb_.size());
+    device_rr_gsb.reserve_unique_modules();
+
+    /* load unique blocks xml file and set up device_rr_gdb */
+    for (pugi::xml_node xml_block_info : xml_root.children()) {
+      /* Error out if the XML child has an invalid name! */
+      if (xml_block_info.name() == std::string("block")) {
+        std::string type =
+          get_attribute(xml_block_info, "type", loc_data).as_string();
+        vtr::Point<size_t> block_coordinate =
+          read_xml_unique_block_coord(xml_block_info, loc_data);
+        std::vector<vtr::Point<size_t>> instance_coords =
+          read_xml_unique_instance_coords(xml_block_info, loc_data);
+
+        /* get block coordinate and instance coordinate, try to setup
+         * device_rr_gsb */
+        if (type == "sb") {
+          device_rr_gsb.preload_unique_sb_module(block_coordinate,
+                                                 instance_coords);
+        } else if (type == "cby") {
+          device_rr_gsb.preload_unique_cby_module(block_coordinate,
+                                                  instance_coords);
+        } else if (type == "cbx") {
+          device_rr_gsb.preload_unique_cbx_module(block_coordinate,
+                                                  instance_coords);
+        } else {
+          archfpga_throw(loc_data.filename_c_str(),
+                         loc_data.line(xml_block_info),
+                         "Invalid block type '%s'\n", type.c_str());
+        }
+      } else {
+        bad_tag(xml_block_info, loc_data, xml_root, {"block"});
+      }
+    }
+    /* As preloading gsb hasn't been developed, we should build gsb using the
+     * preloaded cbs and sbs*/
+    device_rr_gsb.build_gsb_unique_module();
+    if (verbose_output) {
+      report_unique_module_status_read(device_rr_gsb, true);
+    }
+    return CMD_EXEC_SUCCESS;
+  } catch (pugiutil::XmlError& e) {
+    archfpga_throw(file_name, e.line(), "%s", e.what());
+  }
+}
+}  // namespace openfpga

openfpga/src/annotation/read_xml_unique_blocks.h

@@ -0,0 +1,39 @@
+#ifndef READ_XML_UNIQUE_BLOCKS_H
+#define READ_XML_UNIQUE_BLOCKS_H
+
+#include <string>
+
+/* Headers from pugi XML library */
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from libarchfpga */
+#include "arch_error.h"
+#include "device_rr_gsb_utils.h"
+
+/********************************************************************
+ * This file includes the top-level functions of this library
+ * which includes:
+ *  -- reads an XML file of unique blocks to the associated
+ * data structures: device_rr_gsb
+ *******************************************************************/
+namespace openfpga {
+
+std::vector<vtr::Point<size_t>> read_xml_unique_instance_coords(
+  const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data);
+
+vtr::Point<size_t> read_xml_unique_block_coord(
+  const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data);
+
+void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb,
+                                      bool verbose_output);
+
+int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name,
+                           bool verbose_output);
+}  // namespace openfpga
+#endif

openfpga/src/annotation/write_xml_unique_blocks.cpp

@@ -0,0 +1,190 @@
+
+#include <string>
+
+/* Headers from pugi XML library */
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from libarchfpga */
+#include "arch_error.h"
+#include "command_exit_codes.h"
+#include "device_rr_gsb_utils.h"
+#include "openfpga_digest.h"
+#include "read_xml_util.h"
+#include "rr_gsb.h"
+#include "write_xml_unique_blocks.h"
+#include "write_xml_utils.h"
+
+/********************************************************************
+ * This file includes the top-level functions of this library
+ * which includes:
+ *  -- write the unique blocks' information in the associated data structures:
+ *device_rr_gsb to a XML file
+ *******************************************************************/
+namespace openfpga {
+
+/*Write unique blocks and their corresponding instances' information from
+ *device_rr_gsb to a XML file*/
+int write_xml_atom_block(std::fstream& fp,
+                         const std::vector<vtr::Point<size_t>>& instance_map,
+                         const vtr::Point<size_t>& unique_block_coord,
+                         std::string type) {
+  if (false == openfpga::valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  openfpga::write_tab_to_file(fp, 1);
+  fp << "<block";
+  write_xml_attribute(fp, "type", type.c_str());
+  write_xml_attribute(fp, "x", unique_block_coord.x());
+  write_xml_attribute(fp, "y", unique_block_coord.y());
+
+  fp << ">"
+     << "\n";
+
+  for (const auto& instance_info : instance_map) {
+    if (instance_info.x() == unique_block_coord.x() &&
+        instance_info.y() == unique_block_coord.y()) {
+      ;
+    } else {
+      openfpga::write_tab_to_file(fp, 2);
+      fp << "<instance";
+      write_xml_attribute(fp, "x", instance_info.x());
+      write_xml_attribute(fp, "y", instance_info.y());
+
+      fp << "/>"
+         << "\n";
+    }
+  }
+  openfpga::write_tab_to_file(fp, 1);
+  fp << "</block>"
+     << "\n";
+  return openfpga::CMD_EXEC_SUCCESS;
+}
+
+/* Report information about written unique blocks */
+void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb,
+                                       bool verbose_output) {
+  /* Report the stats */
+  VTR_LOGV(
+    verbose_output,
+    "Write %lu unique X-direction connection blocks from a total of %d "
+    "(compression rate=%.2f%)\n",
+    device_rr_gsb.get_num_cb_unique_module(CHANX),
+    find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX),
+    100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX) /
+              (float)device_rr_gsb.get_num_cb_unique_module(CHANX) -
+            1.));
+
+  VTR_LOGV(
+    verbose_output,
+    "Write %lu unique Y-direction connection blocks from a total of %d "
+    "(compression rate=%.2f%)\n",
+    device_rr_gsb.get_num_cb_unique_module(CHANY),
+    find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY),
+    100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY) /
+              (float)device_rr_gsb.get_num_cb_unique_module(CHANY) -
+            1.));
+
+  VTR_LOGV(verbose_output,
+           "Write %lu unique switch blocks from a total of %d (compression "
+           "rate=%.2f%)\n",
+           device_rr_gsb.get_num_sb_unique_module(),
+           find_device_rr_gsb_num_sb_modules(device_rr_gsb,
+                                             g_vpr_ctx.device().rr_graph),
+           100. * ((float)find_device_rr_gsb_num_sb_modules(
+                     device_rr_gsb, g_vpr_ctx.device().rr_graph) /
+                     (float)device_rr_gsb.get_num_sb_unique_module() -
+                   1.));
+
+  VTR_LOG(
+    "Write %lu unique general switch blocks from a total of %d "
+    "(compression "
+    "rate=%.2f%)\n",
+    device_rr_gsb.get_num_gsb_unique_module(),
+    find_device_rr_gsb_num_gsb_modules(device_rr_gsb,
+                                       g_vpr_ctx.device().rr_graph),
+    100. * ((float)find_device_rr_gsb_num_gsb_modules(
+              device_rr_gsb, g_vpr_ctx.device().rr_graph) /
+              (float)device_rr_gsb.get_num_gsb_unique_module() -
+            1.));
+}
+
+/*Top level function to write the xml file of unique blocks*/
+int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname,
+                            bool verbose_output) {
+  vtr::ScopedStartFinishTimer timer("Write unique blocks...");
+  if (device_rr_gsb.is_compressed() == false) {
+    VTR_LOG_ERROR("unique_blocks are empty!");
+    return CMD_EXEC_FATAL_ERROR;
+  }
+  /* Create a file handler */
+  std::fstream fp;
+  /* Open the file stream */
+  fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  openfpga::check_file_stream(fname, fp);
+
+  /* Write the root node */
+  fp << "<unique_blocks>"
+     << "\n";
+
+  for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) {
+    const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id);
+    const std::vector<vtr::Point<size_t>> instance_map =
+      device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord);
+    int status_code =
+      write_xml_atom_block(fp, instance_map, unique_block_coord, "sb");
+    if (status_code != 0) {
+      VTR_LOG_ERROR("write sb unique blocks into xml file failed!");
+      return CMD_EXEC_FATAL_ERROR;
+    }
+  }
+
+  for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX);
+       ++id) {
+    const auto unique_block_coord =
+      device_rr_gsb.get_cbx_unique_block_coord(id);
+    const std::vector<vtr::Point<size_t>> instance_map =
+      device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord);
+    int status_code =
+      write_xml_atom_block(fp, instance_map, unique_block_coord, "cbx");
+    if (status_code != 0) {
+      VTR_LOG_ERROR("write cbx unique blocks into xml file failed!");
+      return CMD_EXEC_FATAL_ERROR;
+    }
+  }
+
+  for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY);
+       ++id) {
+    const auto unique_block_coord =
+      device_rr_gsb.get_cby_unique_block_coord(id);
+    const std::vector<vtr::Point<size_t>> instance_map =
+      device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord);
+    int status_code =
+      write_xml_atom_block(fp, instance_map, unique_block_coord, "cby");
+    if (status_code != 0) {
+      VTR_LOG_ERROR("write cby unique blocks into xml file failed!");
+      return CMD_EXEC_FATAL_ERROR;
+    }
+  }
+
+  /* Finish writing the root node */
+  fp << "</unique_blocks>"
+     << "\n";
+
+  /* Close the file stream */
+  fp.close();
+  if (verbose_output) {
+    report_unique_module_status_write(device_rr_gsb, true);
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+}  // namespace openfpga

openfpga/src/annotation/write_xml_unique_blocks.h

@@ -0,0 +1,37 @@
+#ifndef WRITE_XML_UNIQUE_BLOCKS_H
+#define WRITE_XML_UNIQUE_BLOCKS_H
+
+#include <string>
+
+/* Headers from pugi XML library */
+#include "pugixml.hpp"
+#include "pugixml_util.hpp"
+
+/* Headers from vtr util library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+#include "vtr_time.h"
+
+/* Headers from libarchfpga */
+#include "arch_error.h"
+#include "device_rr_gsb_utils.h"
+
+/********************************************************************
+ * This file includes the top-level functions of this library
+ * which includes:
+ *  -- write the unique blocks' information in the associated data structures:
+ *device_rr_gsb to a XML file
+ *******************************************************************/
+
+namespace openfpga {
+int write_xml_atom_block(std::fstream& fp,
+                         const std::vector<vtr::Point<size_t>>& instance_map,
+                         const vtr::Point<size_t>& unique_block_coord,
+                         std::string type);
+void report_unique_module_status_write(
+  const DeviceRRGSB& device_rr_gsb,
+  bool verbose_output); /*report status of written info*/
+int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname,
+                            bool verbose_output);
+}  // namespace openfpga
+#endif

openfpga/src/base/openfpga_build_fabric_template.h

@@ -20,12 +20,14 @@
 #include "read_xml_io_name_map.h"
 #include "read_xml_module_name_map.h"
 #include "read_xml_tile_config.h"
+#include "read_xml_unique_blocks.h"
 #include "rename_modules.h"
 #include "report_reference.h"
 #include "vtr_log.h"
 #include "vtr_time.h"
 #include "write_xml_fabric_pin_physical_location.h"
 #include "write_xml_module_name_map.h"
+#include "write_xml_unique_blocks.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -124,13 +126,6 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
         cmd.option_name(opt_duplicate_grid_pin).c_str());
       return CMD_EXEC_FATAL_ERROR;
     }
-    if (!cmd_context.option_enable(cmd, opt_compress_routing)) {
-      VTR_LOG_ERROR(
-        "Option '%s' requires options '%s' to be enabled due to a conflict!\n",
-        cmd.option_name(opt_group_tile).c_str(),
-        cmd.option_name(opt_compress_routing).c_str());
-      return CMD_EXEC_FATAL_ERROR;
-    }
   }
   /* Conflicts: duplicate_grid_pin does not support any port merge */
   if (cmd_context.option_enable(cmd, opt_duplicate_grid_pin)) {
@@ -143,13 +138,24 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
     }
   }
 
-  if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
+  if (true == cmd_context.option_enable(cmd, opt_compress_routing) &&
+      false == openfpga_ctx.device_rr_gsb().is_compressed()) {
     compress_routing_hierarchy_template<T>(
       openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
     /* Update flow manager to enable compress routing */
     openfpga_ctx.mutable_flow_manager().set_compress_routing(true);
+  } else if (true == openfpga_ctx.device_rr_gsb().is_compressed()) {
+    openfpga_ctx.mutable_flow_manager().set_compress_routing(true);
   }
 
+  if (cmd_context.option_enable(cmd, opt_group_tile)) {
+    if (!openfpga_ctx.device_rr_gsb().is_compressed()) {
+      VTR_LOG_ERROR(
+        "Option '%s' requires unique blocks to be valid due to a conflict!\n",
+        cmd.option_name(opt_group_tile).c_str());
+      return CMD_EXEC_FATAL_ERROR;
+    }
+  }
   VTR_LOG("\n");
 
   /* Record the execution status in curr_status for each command
@@ -175,7 +181,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
    */
   TileConfig tile_config;
   if (cmd_context.option_enable(cmd, opt_group_tile)) {
-    if (!cmd_context.option_enable(cmd, opt_compress_routing)) {
+    if (!openfpga_ctx.device_rr_gsb().is_compressed()) {
       VTR_LOG_ERROR(
         "Group tile is applicable only when compress routing is enabled!\n");
       return CMD_EXEC_FATAL_ERROR;
@@ -193,7 +199,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd,
     openfpga_ctx.mutable_fabric_tile(), openfpga_ctx.mutable_module_name_map(),
     const_cast<const T&>(openfpga_ctx), g_vpr_ctx.device(),
     cmd_context.option_enable(cmd, opt_frame_view),
-    cmd_context.option_enable(cmd, opt_compress_routing),
+    openfpga_ctx.device_rr_gsb().is_compressed(),
     cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
     predefined_fabric_key, tile_config,
     cmd_context.option_enable(cmd, opt_group_config_block),
@@ -473,6 +479,61 @@ int write_fabric_pin_physical_location_template(
     cmd_context.option_enable(cmd, opt_verbose));
 }
 
+template <class T>
+int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd,
+                                const CommandContext& cmd_context) {
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_file = cmd.option("file");
+  CommandOptionId opt_type = cmd.option("type");
+
+  /* Check the option '--file' is enabled or not
+   * Actually, it must be enabled as the shell interface will check
+   * before reaching this fuction
+   */
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string file_name = cmd_context.option_value(cmd, opt_file);
+  std::string file_type = cmd_context.option_value(cmd, opt_type);
+  /* read unique blocks from a file */
+  if (file_type == "xml") {
+    return read_xml_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(),
+                                  file_name.c_str(),
+                                  cmd_context.option_enable(cmd, opt_verbose));
+  } else {
+    VTR_LOG_ERROR("file type %s not supported", file_type.c_str());
+    return CMD_EXEC_FATAL_ERROR;
+  }
+}
+
+template <class T>
+int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd,
+                                 const CommandContext& cmd_context) {
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_file = cmd.option("file");
+  CommandOptionId opt_type = cmd.option("type");
+
+  /* Check the option '--file' is enabled or not
+   * Actually, it must be enabled as the shell interface will check
+   * before reaching this fuction
+   */
+  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
+  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
+
+  std::string file_name = cmd_context.option_value(cmd, opt_file);
+  std::string file_type = cmd_context.option_value(cmd, opt_type);
+  /* Write unique blocks to a file */
+  /* add check flag */
+  if (file_type == "xml") {
+    return write_xml_unique_blocks(openfpga_ctx.device_rr_gsb(),
+                                   file_name.c_str(),
+                                   cmd_context.option_enable(cmd, opt_verbose));
+  } else {
+    VTR_LOG_ERROR("file type %s not supported", file_type.c_str());
+    return CMD_EXEC_FATAL_ERROR;
+  }
+}
+
 /********************************************************************
  *  Report reference to a file
  *******************************************************************/
@@ -482,14 +543,10 @@ int report_reference_template(const T& openfpga_ctx, const Command& cmd,
   CommandOptionId opt_verbose = cmd.option("verbose");
   CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
 
-  /* Check the option '--file' is enabled or not
-   * Actually, it must be enabled as the shell interface will check
-   * before reaching this fuction
-   */
   CommandOptionId opt_file = cmd.option("file");
+
   VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
   VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
-
   std::string file_name = cmd_context.option_value(cmd, opt_file);
 
   std::string module_name("*"); /* Use a wildcard for everything */
@@ -497,7 +554,6 @@ int report_reference_template(const T& openfpga_ctx, const Command& cmd,
   if (true == cmd_context.option_enable(cmd, opt_module)) {
     module_name = cmd_context.option_value(cmd, opt_module);
   }
-
   /* Write hierarchy to a file */
   return report_reference(file_name.c_str(), module_name,
                           openfpga_ctx.module_graph(),

openfpga/src/base/openfpga_setup_command_template.h

@@ -938,11 +938,89 @@ ShellCommandId add_write_fabric_pin_physical_location_command_template(
 }
 
 /********************************************************************
- * - Add a command to Shell environment: report_reference
+ * - Add a command to Shell environment: read_unique_blocks
  * - Add associated options
  * - Add command dependency
  *******************************************************************/
 template <class T>
+ShellCommandId add_read_unique_blocks_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("read_unique_blocks");
+
+  /* Add an option '--file' */
+  CommandOptionId opt_file = shell_cmd.add_option(
+    "file", true, "specify the file which contains unique block information");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--type' */
+  CommandOptionId opt_type =
+    shell_cmd.add_option("type", true,
+                         "Specify the type of the unique blocks file "
+                         "[xml|bin]. If not specified, by default it is XML.");
+  shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'compact_routing_hierarchy' to the Shell */
+  ShellCommandId shell_cmd_id =
+    shell.add_command(shell_cmd, "Preload unique blocks from xml file", hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id,
+                                     read_unique_blocks_template<T>);
+
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/********************************************************************
+ * - Add a command to Shell environment: write_unique_blocks
+ * - Add associated options
+ * - Add command dependency
+ *******************************************************************/
+template <class T>
+ShellCommandId add_write_unique_blocks_command_template(
+  openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
+  const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
+  Command shell_cmd("write_unique_blocks");
+
+  /* Add an option '--file' */
+  CommandOptionId opt_file = shell_cmd.add_option(
+    "file", true,
+    "specify the file which we will write unique block information to");
+  shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
+
+  /* Add an option '--type' */
+  CommandOptionId opt_type =
+    shell_cmd.add_option("type", true,
+                         "Specify the type of the unique blocks file "
+                         "[xml|bin]. If not specified, by default it is XML.");
+  shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING);
+
+  /* Add an option '--verbose' */
+  shell_cmd.add_option("verbose", false, "Show verbose outputs");
+
+  /* Add command 'compact_routing_hierarchy' to the Shell */
+  ShellCommandId shell_cmd_id =
+    shell.add_command(shell_cmd, "Write unique blocks to a xml file", hidden);
+  shell.set_command_class(shell_cmd_id, cmd_class_id);
+  shell.set_command_execute_function(shell_cmd_id,
+                                     write_unique_blocks_template<T>);
+  /* Add command dependency to the Shell */
+  shell.set_command_dependency(shell_cmd_id, dependent_cmds);
+
+  return shell_cmd_id;
+}
+
+/******************************************************************
+ * - Add a command to Shell environment: report_reference
+ * - Add associated options
+ * - Add command dependency
+ ******************************************************************/
+template <class T>
 ShellCommandId add_report_reference_command_template(
   openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
   const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
@@ -975,7 +1053,6 @@ ShellCommandId add_report_reference_command_template(
   shell.set_command_class(shell_cmd_id, cmd_class_id);
   shell.set_command_const_execute_function(shell_cmd_id,
                                            report_reference_template<T>);
-
   /* Add command dependency to the Shell */
   shell.set_command_dependency(shell_cmd_id, dependent_cmds);
 
@@ -1242,8 +1319,24 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
   cmd_dependency_report_reference.push_back(build_fabric_cmd_id);
   add_report_reference_command_template<T>(
     shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden);
-}
 
+  /********************************
+   * Command 'read_unique_blocks'
+   */
+  /* The command should NOT be executed before
+   * 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency_read_unique_blocks_command;
+  cmd_dependency_read_unique_blocks_command.push_back(link_arch_cmd_id);
+  add_read_unique_blocks_command_template<T>(
+    shell, openfpga_setup_cmd_class, cmd_dependency_read_unique_blocks_command,
+    hidden);
+
+  /********************************
+   * Command 'write_unique_blocks'
+   */
+  add_write_unique_blocks_command_template<T>(
+    shell, openfpga_setup_cmd_class, std::vector<ShellCommandId>(), hidden);
+}
 } /* end namespace openfpga */
 
 #endif

openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga

@@ -0,0 +1,52 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# preload unique blocks from the provided xml file 
+read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing  #--verbose
+
+#write unique blocks xml file 
+write_unique_blocks --file ./write_unique_block.xml --verbose --type xml
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Write the fabric I/O attributes to a file
+# This is used by pin constraint files
+write_fabric_io_info --file ./fabric_io_location.xml --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga

@@ -0,0 +1,79 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Optionally pb pin fixup
+${OPENFPGA_PB_PIN_FIXUP_COMMAND}
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# preload unique blocks from the provided xml file 
+read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+# FIXME: Not supported yet. 
+#write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga

@@ -0,0 +1,82 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Optionally pb pin fixup
+${OPENFPGA_PB_PIN_FIXUP_COMMAND}
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# preload unique blocks from the provided xml file 
+read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric  --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose
+
+#write unique blocks to a xml format file 
+write_unique_blocks --file ./write_unique_block.xml --verbose --type xml
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+# FIXME: Not supported yet. 
+#write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga

@@ -0,0 +1,49 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+#write unique blocks xml file 
+write_unique_blocks --file ./write_unique_block.xml --verbose --type xml
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Write the fabric I/O attributes to a file
+# This is used by pin constraint files
+write_fabric_io_info --file ./fabric_io_location.xml --verbose
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga

@@ -0,0 +1,80 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Optionally pb pin fixup
+${OPENFPGA_PB_PIN_FIXUP_COMMAND}
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose
+
+#write unique blocks xml file 
+write_unique_blocks --file ./write_unique_block.xml --verbose --type xml
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC  ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
+write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} 
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+# FIXME: Not supported yet. 
+#write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -18,6 +18,14 @@ echo -e "Testing preloading rr_graph"
 run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@
 run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@
 
+echo -e "Testing preloading unique blocks"
+run-task basic_tests/preload_unique_blocks/write_unique_blocks $@
+run-task basic_tests/preload_unique_blocks/read_unique_blocks $@
+run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@
+run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@
+run-task basic_tests/preload_unique_blocks/read_write_unique_blocks $@
+
+
 echo -e "Testing testbenches using fpga core wrapper"
 run-task basic_tests/full_testbench/fpga_core_wrapper $@
 run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf

@@ -0,0 +1,35 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml

@@ -0,0 +1,22 @@
+<unique_blocks>
+	<block type="sb" x="0" y="0">
+	</block>
+	<block type="sb" x="0" y="1">
+	</block>
+	<block type="sb" x="1" y="0">
+	</block>
+	<block type="sb" x="1" y="1">
+	</block>
+	<block type="cbx" x="1" y="0">
+		<instance x="0" y="0"/>
+		<instance x="0" y="1"/>
+	</block>
+	<block type="cbx" x="1" y="1">
+	</block>
+	<block type="cby" x="0" y="1">
+		<instance x="0" y="0"/>
+		<instance x="1" y="0"/>
+	</block>
+	<block type="cby" x="1" y="1">
+	</block>
+</unique_blocks>

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf

@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml
+openfpga_vpr_extra_options=
+openfpga_pb_pin_fixup_command=
+openfpga_vpr_device=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=--explicit_port_mapping
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml

@@ -0,0 +1 @@
+<tiles style="top_left"/>

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml

@@ -0,0 +1,92 @@
+<unique_blocks>
+	<block type="sb" x="0" y="0">
+	</block>
+	<block type="sb" x="0" y="1">
+		<instance x="0" y="2"/>
+		<instance x="0" y="3"/>
+	</block>
+	<block type="sb" x="0" y="4">
+	</block>
+	<block type="sb" x="1" y="0">
+		<instance x="2" y="0"/>
+		<instance x="3" y="0"/>
+	</block>
+	<block type="sb" x="1" y="1">
+		<instance x="1" y="2"/>
+		<instance x="1" y="3"/>
+		<instance x="2" y="1"/>
+		<instance x="2" y="2"/>
+		<instance x="2" y="3"/>
+		<instance x="3" y="1"/>
+		<instance x="3" y="2"/>
+		<instance x="3" y="3"/>
+	</block>
+	<block type="sb" x="1" y="4">
+		<instance x="2" y="4"/>
+		<instance x="3" y="4"/>
+	</block>
+	<block type="sb" x="4" y="0">
+	</block>
+	<block type="sb" x="4" y="1">
+		<instance x="4" y="2"/>
+		<instance x="4" y="3"/>
+	</block>
+	<block type="sb" x="4" y="4">
+	</block>
+	<block type="cbx" x="1" y="0">
+		<instance x="0" y="0"/>
+		<instance x="0" y="1"/>
+		<instance x="0" y="2"/>
+		<instance x="0" y="3"/>
+		<instance x="0" y="4"/>
+		<instance x="2" y="0"/>
+		<instance x="3" y="0"/>
+		<instance x="4" y="0"/>
+	</block>
+	<block type="cbx" x="1" y="1">
+		<instance x="1" y="2"/>
+		<instance x="1" y="3"/>
+		<instance x="2" y="1"/>
+		<instance x="2" y="2"/>
+		<instance x="2" y="3"/>
+		<instance x="3" y="1"/>
+		<instance x="3" y="2"/>
+		<instance x="3" y="3"/>
+		<instance x="4" y="1"/>
+		<instance x="4" y="2"/>
+		<instance x="4" y="3"/>
+	</block>
+	<block type="cbx" x="1" y="4">
+		<instance x="2" y="4"/>
+		<instance x="3" y="4"/>
+		<instance x="4" y="4"/>
+	</block>
+	<block type="cby" x="0" y="1">
+		<instance x="0" y="0"/>
+		<instance x="0" y="2"/>
+		<instance x="0" y="3"/>
+		<instance x="0" y="4"/>
+		<instance x="1" y="0"/>
+		<instance x="2" y="0"/>
+		<instance x="3" y="0"/>
+		<instance x="4" y="0"/>
+	</block>
+	<block type="cby" x="1" y="1">
+		<instance x="1" y="2"/>
+		<instance x="1" y="3"/>
+		<instance x="1" y="4"/>
+		<instance x="2" y="1"/>
+		<instance x="2" y="2"/>
+		<instance x="2" y="3"/>
+		<instance x="2" y="4"/>
+		<instance x="3" y="1"/>
+		<instance x="3" y="2"/>
+		<instance x="3" y="3"/>
+		<instance x="3" y="4"/>
+	</block>
+	<block type="cby" x="4" y="1">
+		<instance x="4" y="2"/>
+		<instance x="4" y="3"/>
+		<instance x="4" y="4"/>
+	</block>
+</unique_blocks>

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf

@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml
+openfpga_vpr_extra_options=
+openfpga_pb_pin_fixup_command=
+openfpga_vpr_device=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=--explicit_port_mapping
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml

@@ -0,0 +1 @@
+<tiles style="top_left"/>

openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml

@@ -0,0 +1,92 @@
+<unique_blocks>
+	<block type="sb" x="0" y="0">
+	</block>
+	<block type="sb" x="0" y="1">
+		<instance x="0" y="2"/>
+		<instance x="0" y="3"/>
+	</block>
+	<block type="sb" x="0" y="4">
+	</block>
+	<block type="sb" x="1" y="0">
+		<instance x="2" y="0"/>
+		<instance x="3" y="0"/>
+	</block>
+	<block type="sb" x="1" y="1">
+		<instance x="1" y="2"/>
+		<instance x="1" y="3"/>
+		<instance x="2" y="1"/>
+		<instance x="2" y="2"/>
+		<instance x="2" y="3"/>
+		<instance x="3" y="1"/>
+		<instance x="3" y="2"/>
+		<instance x="3" y="3"/>
+	</block>
+	<block type="sb" x="1" y="4">
+		<instance x="2" y="4"/>
+		<instance x="3" y="4"/>
+	</block>
+	<block type="sb" x="4" y="0">
+	</block>
+	<block type="sb" x="4" y="1">
+		<instance x="4" y="2"/>
+		<instance x="4" y="3"/>
+	</block>
+	<block type="sb" x="4" y="4">
+	</block>
+	<block type="cbx" x="1" y="0">
+		<instance x="0" y="0"/>
+		<instance x="0" y="1"/>
+		<instance x="0" y="2"/>
+		<instance x="0" y="3"/>
+		<instance x="0" y="4"/>
+		<instance x="2" y="0"/>
+		<instance x="3" y="0"/>
+		<instance x="4" y="0"/>
+	</block>
+	<block type="cbx" x="1" y="1">
+		<instance x="1" y="2"/>
+		<instance x="1" y="3"/>
+		<instance x="2" y="1"/>
+		<instance x="2" y="2"/>
+		<instance x="2" y="3"/>
+		<instance x="3" y="1"/>
+		<instance x="3" y="2"/>
+		<instance x="3" y="3"/>
+		<instance x="4" y="1"/>
+		<instance x="4" y="2"/>
+		<instance x="4" y="3"/>
+	</block>
+	<block type="cbx" x="1" y="4">
+		<instance x="2" y="4"/>
+		<instance x="3" y="4"/>
+		<instance x="4" y="4"/>
+	</block>
+	<block type="cby" x="0" y="1">
+		<instance x="0" y="0"/>
+		<instance x="0" y="2"/>
+		<instance x="0" y="3"/>
+		<instance x="0" y="4"/>
+		<instance x="1" y="0"/>
+		<instance x="2" y="0"/>
+		<instance x="3" y="0"/>
+		<instance x="4" y="0"/>
+	</block>
+	<block type="cby" x="1" y="1">
+		<instance x="1" y="2"/>
+		<instance x="1" y="3"/>
+		<instance x="1" y="4"/>
+		<instance x="2" y="1"/>
+		<instance x="2" y="2"/>
+		<instance x="2" y="3"/>
+		<instance x="2" y="4"/>
+		<instance x="3" y="1"/>
+		<instance x="3" y="2"/>
+		<instance x="3" y="3"/>
+		<instance x="3" y="4"/>
+	</block>
+	<block type="cby" x="4" y="1">
+		<instance x="4" y="2"/>
+		<instance x="4" y="3"/>
+		<instance x="4" y="4"/>
+	</block>
+</unique_blocks>

openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf

@@ -0,0 +1,35 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+

openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf

@@ -0,0 +1,41 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_extra_options=
+openfpga_pb_pin_fixup_command=
+openfpga_vpr_device=4x4
+openfpga_vpr_route_chan_width=20
+openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=--explicit_port_mapping
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml

@@ -0,0 +1 @@
+<tiles style="top_left"/>