From 48a386c9b63a25401a8002a6545522093de4cb5b Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 2 Aug 2024 01:43:01 -0700 Subject: [PATCH 01/50] add read and write uniqueblocks commands --- .../src/base/openfpga_build_fabric_template.h | 44 +++++++ .../base/openfpga_setup_command_template.h | 88 +++++++++++++- .../src/fabric/read_xml_unique_blocks.cpp | 112 ++++++++++++++++++ openfpga/src/fabric/read_xml_unique_blocks.h | 16 +++ 4 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 openfpga/src/fabric/read_xml_unique_blocks.cpp create mode 100644 openfpga/src/fabric/read_xml_unique_blocks.h diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index b36903a22..193aa0fef 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -25,6 +25,7 @@ #include "vtr_time.h" #include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" +#include "read_xml_unique_blocks.h" /* begin namespace openfpga */ namespace openfpga { @@ -472,6 +473,49 @@ int write_fabric_pin_physical_location_template( cmd_context.option_enable(cmd, opt_verbose)); } +template +int read_unique_blocks_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_type = cmd.option("type"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + std::string file_type = cmd_context.option_value(cmd, opt_type); + /* Write hierarchy to a file */ + return read_xml_unique_blocks(file_name.c_str(), file_type.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); +} + +template +int write_unique_blocks_template(const T& openfpga_ctx, const Command& cmd, + const CommandContext& cmd_context) { + CommandOptionId opt_verbose = cmd.option("verbose"); + CommandOptionId opt_file = cmd.option("file"); + CommandOptionId opt_type = cmd.option("type"); + + /* Check the option '--file' is enabled or not + * Actually, it must be enabled as the shell interface will check + * before reaching this fuction + */ + VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); + VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); + + std::string file_name = cmd_context.option_value(cmd, opt_file); + std::string file_type = cmd_context.option_value(cmd, opt_type); + + /* Write hierarchy to a file */ + return read_xml_unique_blocks(file_name.c_str(), file_type.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); +} + } /* end namespace openfpga */ #endif diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 3d178ee17..42816029c 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -924,6 +924,79 @@ ShellCommandId add_write_fabric_pin_physical_location_command_template( return shell_cmd_id; } + +/******************************************************************** + * - Add a command to Shell environment: read_unique_blocks + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_read_unique_blocks_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("read_unique_blocks"); + + /* Add an option '--file' */ + shell_cmd.add_option( + "file", true, + "unique blocks xml file"); + + /* Add an option '--type' */ + shell_cmd.add_option("type", true, + "the file type of input file"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'compact_routing_hierarchy' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Preload unique blocks from xml file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, read_unique_blocks_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + + +/******************************************************************** + * - Add a command to Shell environment: write_unique_blocks + * - Add associated options + * - Add command dependency + *******************************************************************/ +template +ShellCommandId add_write_unique_blocks_command_template( + openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, + const std::vector& dependent_cmds, const bool& hidden) { + Command shell_cmd("write_unique_blocks"); + + /* Add an option '--file' */ + shell_cmd.add_option( + "file", true, + "unique blocks xml file"); + + /* Add an option '--type' */ + shell_cmd.add_option("type", true, + "the file type of input file"); + + /* Add an option '--verbose' */ + shell_cmd.add_option("verbose", false, "Show verbose outputs"); + + /* Add command 'compact_routing_hierarchy' to the Shell */ + ShellCommandId shell_cmd_id = shell.add_command( + shell_cmd, "Preload unique blocks from xml file", hidden); + shell.set_command_class(shell_cmd_id, cmd_class_id); + shell.set_command_execute_function(shell_cmd_id, write_unique_blocks_template); + + /* Add command dependency to the Shell */ + shell.set_command_dependency(shell_cmd_id, dependent_cmds); + + return shell_cmd_id; +} + + template void add_setup_command_templates(openfpga::Shell& shell, const bool& hidden = false) { @@ -1175,8 +1248,21 @@ void add_setup_command_templates(openfpga::Shell& shell, add_write_fabric_pin_physical_location_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_write_fabric_pin_physical_location, hidden); -} + /******************************** + * Command 'read_unique_blocks' + */ + add_read_unique_blocks_command_template( + shell, openfpga_setup_cmd_class, std::vector(), hidden); + + /******************************** + * Command 'write_unique_blocks' + */ + add_write_unique_blocks_command_template( + shell, openfpga_setup_cmd_class, std::vector(), hidden); + + +} } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp new file mode 100644 index 000000000..8b80f7a3e --- /dev/null +++ b/openfpga/src/fabric/read_xml_unique_blocks.cpp @@ -0,0 +1,112 @@ +/******************************************************************** + * This file includes the top-level function of this library + * which reads an XML of a fabric key to the associated + * data structures + *******************************************************************/ +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libopenfpga util library */ +#include "openfpga_port_parser.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "read_xml_unique_blocks.h" +#include "read_xml_util.h" + +/******************************************************************** + * Parse XML codes of a to an object of FabricKey + *******************************************************************/ +static void read_xml_unique_block_info( + pugi::xml_node& xml_pin_constraint, const pugiutil::loc_data& loc_data) { + std::string pass = "pass here"; +// /* Create a new design constraint in the storage */ +// RepackDesignConstraintId design_constraint_id = +// repack_design_constraints.create_design_constraint( +// RepackDesignConstraints::IGNORE_NET); + +// if (false == repack_design_constraints.valid_design_constraint_id( +// design_constraint_id)) { +// archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), +// "Fail to create design constraint!\n"); +// } + +// std::string pin_ctx_to_parse = +// get_attribute(xml_pin_constraint, "pin", loc_data).as_string(); +// openfpga::StringToken pin_tokenizer(pin_ctx_to_parse); +// std::vector pin_info = pin_tokenizer.split('.'); +// /* Expect two contents, otherwise error out */ +// if (pin_info.size() != 2) { +// std::string err_msg = +// std::string("Invalid content '") + pin_ctx_to_parse + +// std::string("' to skip, expect .\n"); +// VTR_LOG_ERROR(err_msg.c_str()); +// VTR_ASSERT(pin_info.size() == 2); +// } +// std::string pb_type_name = pin_info[0]; +// openfpga::PortParser port_parser(pin_info[1]); +// openfpga::BasicPort curr_port = port_parser.port(); +// if (!curr_port.is_valid()) { +// std::string err_msg = +// std::string("Invalid pin definition '") + pin_ctx_to_parse + +// std::string("', expect .[int:int]\n"); +// VTR_LOG_ERROR(err_msg.c_str()); +// VTR_ASSERT(curr_port.is_valid()); +// } +// repack_design_constraints.set_pb_type(design_constraint_id, pb_type_name); +// repack_design_constraints.set_pin(design_constraint_id, curr_port); +// repack_design_constraints.set_net( +// design_constraint_id, +// get_attribute(xml_pin_constraint, "name", loc_data).as_string()); +} + +/******************************************************************** + * Parse XML codes about to an object of + *RepackDesignConstraints + *******************************************************************/ +int read_xml_unique_blocks(const char* file_name, const char* file_type, + bool verbose) { + vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); + +// RepackDesignConstraints repack_design_constraints; + + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + + try { + loc_data = pugiutil::load_xml(doc, file_name); + + pugi::xml_node xml_root = + get_single_child(doc, "unique_blocks", loc_data); + + // size_t num_design_constraints = + // std::distance(xml_root.children().begin(), xml_root.children().end()); + // /* Reserve memory space for the region */ + // repack_design_constraints.reserve_design_constraints( + // num_design_constraints); + + for (pugi::xml_node xml_block_info : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_block_info.name() == std::string("block")) { + read_xml_unique_block_info(xml_block_info, loc_data); + } else { + bad_tag(xml_block_info, loc_data, xml_root, + {"block"}); + return 1; + } + } + } catch (pugiutil::XmlError& e) { + archfpga_throw(file_name, e.line(), "%s", e.what()); + } + + return 0; +} diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h new file mode 100644 index 000000000..cd89ff801 --- /dev/null +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -0,0 +1,16 @@ +#ifndef READ_XML_UNIQUE_BLOCKS_H +#define READ_XML_UNIQUE_BLOCKS_H + +/******************************************************************** + * Include header files that are required by function declaration + *******************************************************************/ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/******************************************************************** + * Function declaration + *******************************************************************/ +int read_xml_unique_blocks(const char* file_name, const char* file_type, + bool verbose); + +#endif From 7f426d59394a760908402cd0d07eca94fc43dfa4 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 2 Aug 2024 03:10:10 -0700 Subject: [PATCH 02/50] add commands --- .../base/openfpga_setup_command_template.h | 47 ++++++++++--------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 42816029c..01e2f78cb 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -924,7 +924,6 @@ ShellCommandId add_write_fabric_pin_physical_location_command_template( return shell_cmd_id; } - /******************************************************************** * - Add a command to Shell environment: read_unique_blocks * - Add associated options @@ -937,22 +936,24 @@ ShellCommandId add_read_unique_blocks_command_template( Command shell_cmd("read_unique_blocks"); /* Add an option '--file' */ - shell_cmd.add_option( - "file", true, - "unique blocks xml file"); + CommandOptionId opt_file = + shell_cmd.add_option("file", true, "specify the unique blocks xml file"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); /* Add an option '--type' */ - shell_cmd.add_option("type", true, - "the file type of input file"); + CommandOptionId opt_type = shell_cmd.add_option( + "type", true, "specify the type of the unique blocks xml file"); + shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); /* Add command 'compact_routing_hierarchy' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "Preload unique blocks from xml file", hidden); + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "Preload unique blocks from xml file", hidden); shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, read_unique_blocks_template); + shell.set_command_execute_function(shell_cmd_id, + read_unique_blocks_template); /* Add command dependency to the Shell */ shell.set_command_dependency(shell_cmd_id, dependent_cmds); @@ -960,7 +961,6 @@ ShellCommandId add_read_unique_blocks_command_template( return shell_cmd_id; } - /******************************************************************** * - Add a command to Shell environment: write_unique_blocks * - Add associated options @@ -973,22 +973,24 @@ ShellCommandId add_write_unique_blocks_command_template( Command shell_cmd("write_unique_blocks"); /* Add an option '--file' */ - shell_cmd.add_option( - "file", true, - "unique blocks xml file"); + CommandOptionId opt_file = + shell_cmd.add_option("file", true, "specify the unique blocks xml file"); + shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); /* Add an option '--type' */ - shell_cmd.add_option("type", true, - "the file type of input file"); + CommandOptionId opt_type = shell_cmd.add_option( + "type", true, "specify the type of the unique blocks xml file"); + shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING); /* Add an option '--verbose' */ shell_cmd.add_option("verbose", false, "Show verbose outputs"); /* Add command 'compact_routing_hierarchy' to the Shell */ - ShellCommandId shell_cmd_id = shell.add_command( - shell_cmd, "Preload unique blocks from xml file", hidden); + ShellCommandId shell_cmd_id = + shell.add_command(shell_cmd, "Preload unique blocks from xml file", hidden); shell.set_command_class(shell_cmd_id, cmd_class_id); - shell.set_command_execute_function(shell_cmd_id, write_unique_blocks_template); + shell.set_command_execute_function(shell_cmd_id, + write_unique_blocks_template); /* Add command dependency to the Shell */ shell.set_command_dependency(shell_cmd_id, dependent_cmds); @@ -996,7 +998,6 @@ ShellCommandId add_write_unique_blocks_command_template( return shell_cmd_id; } - template void add_setup_command_templates(openfpga::Shell& shell, const bool& hidden = false) { @@ -1253,15 +1254,15 @@ void add_setup_command_templates(openfpga::Shell& shell, * Command 'read_unique_blocks' */ add_read_unique_blocks_command_template( - shell, openfpga_setup_cmd_class, std::vector(), hidden); + shell, openfpga_setup_cmd_class, std::vector(), + hidden); /******************************** * Command 'write_unique_blocks' */ add_write_unique_blocks_command_template( - shell, openfpga_setup_cmd_class, std::vector(), hidden); - - + shell, openfpga_setup_cmd_class, std::vector(), + hidden); } } /* end namespace openfpga */ From 5ac19ea62866601f6527742546a38616a4835218 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 4 Aug 2024 20:51:27 -0700 Subject: [PATCH 03/50] read unique blocks io --- .../src/fabric/read_xml_unique_blocks.cpp | 73 ++++++------------- 1 file changed, 24 insertions(+), 49 deletions(-) diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp index 8b80f7a3e..87845f617 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.cpp +++ b/openfpga/src/fabric/read_xml_unique_blocks.cpp @@ -1,6 +1,6 @@ /******************************************************************** * This file includes the top-level function of this library - * which reads an XML of a fabric key to the associated + * which reads an XML of unique routing blocks to the associated * data structures *******************************************************************/ #include @@ -23,49 +23,13 @@ #include "read_xml_util.h" /******************************************************************** - * Parse XML codes of a to an object of FabricKey + * Parse XML codes of a to an object of unique_blocks *******************************************************************/ -static void read_xml_unique_block_info( - pugi::xml_node& xml_pin_constraint, const pugiutil::loc_data& loc_data) { - std::string pass = "pass here"; -// /* Create a new design constraint in the storage */ -// RepackDesignConstraintId design_constraint_id = -// repack_design_constraints.create_design_constraint( -// RepackDesignConstraints::IGNORE_NET); - -// if (false == repack_design_constraints.valid_design_constraint_id( -// design_constraint_id)) { -// archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_pin_constraint), -// "Fail to create design constraint!\n"); -// } - -// std::string pin_ctx_to_parse = -// get_attribute(xml_pin_constraint, "pin", loc_data).as_string(); -// openfpga::StringToken pin_tokenizer(pin_ctx_to_parse); -// std::vector pin_info = pin_tokenizer.split('.'); -// /* Expect two contents, otherwise error out */ -// if (pin_info.size() != 2) { -// std::string err_msg = -// std::string("Invalid content '") + pin_ctx_to_parse + -// std::string("' to skip, expect .\n"); -// VTR_LOG_ERROR(err_msg.c_str()); -// VTR_ASSERT(pin_info.size() == 2); -// } -// std::string pb_type_name = pin_info[0]; -// openfpga::PortParser port_parser(pin_info[1]); -// openfpga::BasicPort curr_port = port_parser.port(); -// if (!curr_port.is_valid()) { -// std::string err_msg = -// std::string("Invalid pin definition '") + pin_ctx_to_parse + -// std::string("', expect .[int:int]\n"); -// VTR_LOG_ERROR(err_msg.c_str()); -// VTR_ASSERT(curr_port.is_valid()); -// } -// repack_design_constraints.set_pb_type(design_constraint_id, pb_type_name); -// repack_design_constraints.set_pin(design_constraint_id, curr_port); -// repack_design_constraints.set_net( -// design_constraint_id, -// get_attribute(xml_pin_constraint, "name", loc_data).as_string()); +static void read_xml_unique_instance_info(pugi::xml_node& xml_instance_info, + const pugiutil::loc_data& loc_data) { + std::string pass = "pass here"; + std::string instance_x = get_attribute(xml_instance_info, "x", loc_data).as_string(); + std::string instance_y = get_attribute(xml_instance_info, "y", loc_data).as_string(); } /******************************************************************** @@ -76,7 +40,7 @@ int read_xml_unique_blocks(const char* file_name, const char* file_type, bool verbose) { vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); -// RepackDesignConstraints repack_design_constraints; + // RepackDesignConstraints repack_design_constraints; /* Parse the file */ pugi::xml_document doc; @@ -85,8 +49,7 @@ int read_xml_unique_blocks(const char* file_name, const char* file_type, try { loc_data = pugiutil::load_xml(doc, file_name); - pugi::xml_node xml_root = - get_single_child(doc, "unique_blocks", loc_data); + pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); // size_t num_design_constraints = // std::distance(xml_root.children().begin(), xml_root.children().end()); @@ -97,12 +60,24 @@ int read_xml_unique_blocks(const char* file_name, const char* file_type, for (pugi::xml_node xml_block_info : xml_root.children()) { /* Error out if the XML child has an invalid name! */ if (xml_block_info.name() == std::string("block")) { - read_xml_unique_block_info(xml_block_info, loc_data); + std::string type = + get_attribute(xml_block_info, "type", loc_data).as_string(); + std::string block_x = + get_attribute(xml_block_info, "x", loc_data).as_string(); + std::string block_y = + get_attribute(xml_block_info, "y", loc_data).as_string(); + for (pugi::xml_node xml_instance_info : xml_block_info.children()) { + if (xml_instance_info.name() == std::string("instance")) { + read_xml_unique_instance_info(xml_instance_info, loc_data); + } + // read_xml_unique_instance_info(xml_instance_info, loc_data); + } } else { - bad_tag(xml_block_info, loc_data, xml_root, - {"block"}); + bad_tag(xml_block_info, loc_data, xml_root, {"block"}); return 1; } + // std::cout << "what is the root name: " << xml_block_info.name() << + // std::endl; } } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); From c726744154d9c03aeea044ddff338212c0c4b2e9 Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 5 Aug 2024 02:23:47 -0700 Subject: [PATCH 04/50] add sb unique modules --- openfpga/src/annotation/device_rr_gsb.cpp | 33 ++++++ openfpga/src/annotation/device_rr_gsb.h | 3 + .../src/base/openfpga_build_fabric_template.h | 8 +- .../src/fabric/read_xml_unique_blocks.cpp | 87 --------------- openfpga/src/fabric/read_xml_unique_blocks.h | 104 +++++++++++++++++- 5 files changed, 141 insertions(+), 94 deletions(-) delete mode 100644 openfpga/src/fabric/read_xml_unique_blocks.cpp diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 963d53bc1..a2ac6df3d 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -560,6 +560,39 @@ size_t DeviceRRGSB::get_cb_unique_module_index( } return cb_unique_module_id; +} + +void DeviceRRGSB::load_unique_cb_module_from_user_input(int x, int y){ + + + + +} + +void DeviceRRGSB::load_unique_sb_module_from_user_input(int ix, int iy){ + vtr::Point sb_coordinate(ix, iy); + bool is_unique_module = true; + + for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { + /* Check whether the input module exists.*/ + if (sb_unique_module_[id].x() == ix && sb_unique_module_[id].y() == iy){ + is_unique_module = false; + sb_unique_module_id_[ix][iy] = id; + break; + } + } + if (true == is_unique_module) { + sb_unique_module_.push_back(sb_coordinate); + /* Record the id of unique mirror */ + sb_unique_module_id_[ix][iy] =sb_unique_module_.size() - 1; + } +} + +void DeviceRRGSB::load_unique_gsb_module_from_user_input(int x, int y){ + + + + } } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 245b1646b..267118e00 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -95,6 +95,9 @@ class DeviceRRGSB { automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ + void load_unique_cb_module_from_user_input(int x, int y); + void load_unique_sb_module_from_user_input(int x, int y); + void load_unique_gsb_module_from_user_input(int x, int y); private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 193aa0fef..3ba3c1d1a 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -474,7 +474,7 @@ int write_fabric_pin_physical_location_template( } template -int read_unique_blocks_template(const T& openfpga_ctx, const Command& cmd, +int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_file = cmd.option("file"); @@ -490,12 +490,12 @@ int read_unique_blocks_template(const T& openfpga_ctx, const Command& cmd, std::string file_name = cmd_context.option_value(cmd, opt_file); std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write hierarchy to a file */ - return read_xml_unique_blocks(file_name.c_str(), file_type.c_str(), + return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } template -int write_unique_blocks_template(const T& openfpga_ctx, const Command& cmd, +int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_file = cmd.option("file"); @@ -512,7 +512,7 @@ int write_unique_blocks_template(const T& openfpga_ctx, const Command& cmd, std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write hierarchy to a file */ - return read_xml_unique_blocks(file_name.c_str(), file_type.c_str(), + return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp deleted file mode 100644 index 87845f617..000000000 --- a/openfpga/src/fabric/read_xml_unique_blocks.cpp +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************** - * This file includes the top-level function of this library - * which reads an XML of unique routing blocks to the associated - * data structures - *******************************************************************/ -#include - -/* Headers from pugi XML library */ -#include "pugixml.hpp" -#include "pugixml_util.hpp" - -/* Headers from vtr util library */ -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from libopenfpga util library */ -#include "openfpga_port_parser.h" - -/* Headers from libarchfpga */ -#include "arch_error.h" -#include "read_xml_unique_blocks.h" -#include "read_xml_util.h" - -/******************************************************************** - * Parse XML codes of a to an object of unique_blocks - *******************************************************************/ -static void read_xml_unique_instance_info(pugi::xml_node& xml_instance_info, - const pugiutil::loc_data& loc_data) { - std::string pass = "pass here"; - std::string instance_x = get_attribute(xml_instance_info, "x", loc_data).as_string(); - std::string instance_y = get_attribute(xml_instance_info, "y", loc_data).as_string(); -} - -/******************************************************************** - * Parse XML codes about to an object of - *RepackDesignConstraints - *******************************************************************/ -int read_xml_unique_blocks(const char* file_name, const char* file_type, - bool verbose) { - vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); - - // RepackDesignConstraints repack_design_constraints; - - /* Parse the file */ - pugi::xml_document doc; - pugiutil::loc_data loc_data; - - try { - loc_data = pugiutil::load_xml(doc, file_name); - - pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); - - // size_t num_design_constraints = - // std::distance(xml_root.children().begin(), xml_root.children().end()); - // /* Reserve memory space for the region */ - // repack_design_constraints.reserve_design_constraints( - // num_design_constraints); - - for (pugi::xml_node xml_block_info : xml_root.children()) { - /* Error out if the XML child has an invalid name! */ - if (xml_block_info.name() == std::string("block")) { - std::string type = - get_attribute(xml_block_info, "type", loc_data).as_string(); - std::string block_x = - get_attribute(xml_block_info, "x", loc_data).as_string(); - std::string block_y = - get_attribute(xml_block_info, "y", loc_data).as_string(); - for (pugi::xml_node xml_instance_info : xml_block_info.children()) { - if (xml_instance_info.name() == std::string("instance")) { - read_xml_unique_instance_info(xml_instance_info, loc_data); - } - // read_xml_unique_instance_info(xml_instance_info, loc_data); - } - } else { - bad_tag(xml_block_info, loc_data, xml_root, {"block"}); - return 1; - } - // std::cout << "what is the root name: " << xml_block_info.name() << - // std::endl; - } - } catch (pugiutil::XmlError& e) { - archfpga_throw(file_name, e.line(), "%s", e.what()); - } - - return 0; -} diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index cd89ff801..a6b7cb168 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -2,15 +2,113 @@ #define READ_XML_UNIQUE_BLOCKS_H /******************************************************************** - * Include header files that are required by function declaration + * This file includes the top-level function of this library + * which reads an XML of unique routing blocks to the associated + * data structures *******************************************************************/ + +#include + +/* Headers from pugi XML library */ #include "pugixml.hpp" #include "pugixml_util.hpp" +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libopenfpga util library */ +#include "openfpga_port_parser.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "read_xml_unique_blocks.h" +#include "read_xml_util.h" +#include "rr_gsb.h" + /******************************************************************** * Function declaration *******************************************************************/ -int read_xml_unique_blocks(const char* file_name, const char* file_type, - bool verbose); +template +int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, + const char* file_type, bool verbose); + +/******************************************************************** + * Parse XML codes of a to an object of unique_blocks + *******************************************************************/ +template +void read_xml_unique_instance_info(T& device_rr_gsb, + pugi::xml_node& xml_instance_info, + const pugiutil::loc_data& loc_data, + std::string type) { + std::string pass = "pass here"; + int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); + int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); + if (type == "sb") { + device_rr_gsb.load_unique_sb_module_from_user_input(instance_x, instance_y); + } else if (type == "cb") { + // read_cb_unique_blocks(); + std::cout << "By pass here" << std::endl; + } else if (type == "gsb") { + std::cout << "By pass here" << std::endl; + // read_gsb_unique_blocks(); + } +} + +/******************************************************************** + * Parse XML codes about to an object of + *RepackDesignConstraints + *******************************************************************/ +template +int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, + const char* file_type, bool verbose) { + vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); + + // RepackDesignConstraints repack_design_constraints; + + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + + try { + loc_data = pugiutil::load_xml(doc, file_name); + + pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); + + /* get device_rr_gsb data type and initialize it*/ + auto device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); + device_rr_gsb.clear(); + + /* load unique blocks xml file and set up device_rr_gdb */ + for (pugi::xml_node xml_block_info : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_block_info.name() == std::string("block")) { + std::string type = + get_attribute(xml_block_info, "type", loc_data).as_string(); + std::string block_x = + get_attribute(xml_block_info, "x", loc_data).as_string(); + std::string block_y = + get_attribute(xml_block_info, "y", loc_data).as_string(); + for (pugi::xml_node xml_instance_info : xml_block_info.children()) { + if (xml_instance_info.name() == std::string("instance")) { + read_xml_unique_instance_info(device_rr_gsb, xml_instance_info, + loc_data, type); + } + // read_xml_unique_instance_info(xml_instance_info, loc_data); + } + } else { + bad_tag(xml_block_info, loc_data, xml_root, {"block"}); + return 1; + } + // std::cout << "what is the root name: " << xml_block_info.name() << + // std::endl; + } + } catch (pugiutil::XmlError& e) { + archfpga_throw(file_name, e.line(), "%s", e.what()); + } + + return 0; +} #endif From 72a90a4d8fdeb86cee0f8d8e6d0f89935f955e27 Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 5 Aug 2024 19:42:21 -0700 Subject: [PATCH 05/50] add preload function --- openfpga/src/annotation/device_rr_gsb.cpp | 49 ++++++++++++++------ openfpga/src/annotation/device_rr_gsb.h | 7 +-- openfpga/src/fabric/read_xml_unique_blocks.h | 4 +- 3 files changed, 41 insertions(+), 19 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index a2ac6df3d..b3189c055 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -562,20 +562,17 @@ size_t DeviceRRGSB::get_cb_unique_module_index( return cb_unique_module_id; } -void DeviceRRGSB::load_unique_cb_module_from_user_input(int x, int y){ +void DeviceRRGSB::preload_unique_cbx_module(int x, int y) {} +void DeviceRRGSB::preload_unique_cby_module(int x, int y) {} - - -} - -void DeviceRRGSB::load_unique_sb_module_from_user_input(int ix, int iy){ +void DeviceRRGSB::preload_unique_sb_module(int ix, int iy) { vtr::Point sb_coordinate(ix, iy); bool is_unique_module = true; - + for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { - /* Check whether the input module exists.*/ - if (sb_unique_module_[id].x() == ix && sb_unique_module_[id].y() == iy){ + /* Check whether the input module exists.*/ + if (sb_unique_module_[id].x() == ix && sb_unique_module_[id].y() == iy) { is_unique_module = false; sb_unique_module_id_[ix][iy] = id; break; @@ -584,15 +581,39 @@ void DeviceRRGSB::load_unique_sb_module_from_user_input(int ix, int iy){ if (true == is_unique_module) { sb_unique_module_.push_back(sb_coordinate); /* Record the id of unique mirror */ - sb_unique_module_id_[ix][iy] =sb_unique_module_.size() - 1; + sb_unique_module_id_[ix][iy] = sb_unique_module_.size() - 1; } } -void DeviceRRGSB::load_unique_gsb_module_from_user_input(int x, int y){ - - - +/* need to preload after cb and sb are preloaded */ +void DeviceRRGSB::preload_unique_gsb_module(int ix, int iy) { + // vtr::Point gsb_coordinate(ix, iy); + // bool is_unique_module = true; + // for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { + // const vtr::Point& gsb_unique_module_coordinate = + // gsb_unique_module_[id]; + // if ((sb_unique_module_id_[ix][iy] == + // sb_unique_module_id_[gsb_unique_module_coordinate.x()] + // [gsb_unique_module_coordinate.y()]) && + // (cbx_unique_module_id_[ix][iy] == + // cbx_unique_module_id_[gsb_unique_module_coordinate.x()] + // [gsb_unique_module_coordinate.y()]) && + // (cby_unique_module_id_[ix][iy] == + // cby_unique_module_id_[gsb_unique_module_coordinate.x()] + // [gsb_unique_module_coordinate.y()])) { + // /* This is a mirror, raise the flag and we finish */ + // is_unique_module = false; + // /* Record the id of unique mirror */ + // gsb_unique_module_id_[ix][iy] = id; + // break; + // } + // } + // if (true == is_unique_module) { + // add_gsb_unique_module(gsb_coordinate); + // /* Record the id of unique mirror */ + // gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1; + // } } } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 267118e00..911ed31c4 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -95,9 +95,10 @@ class DeviceRRGSB { automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ - void load_unique_cb_module_from_user_input(int x, int y); - void load_unique_sb_module_from_user_input(int x, int y); - void load_unique_gsb_module_from_user_input(int x, int y); + void preload_unique_cbx_module(int x, int y); + void preload_unique_cby_module(int x, int y); + void preload_unique_sb_module(int x, int y); + void preload_unique_gsb_module(int x, int y); private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index a6b7cb168..b9b17ce91 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -42,15 +42,15 @@ void read_xml_unique_instance_info(T& device_rr_gsb, pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data, std::string type) { - std::string pass = "pass here"; int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); if (type == "sb") { - device_rr_gsb.load_unique_sb_module_from_user_input(instance_x, instance_y); + device_rr_gsb.preload_unique_sb_module(instance_x, instance_y); } else if (type == "cb") { // read_cb_unique_blocks(); std::cout << "By pass here" << std::endl; } else if (type == "gsb") { + /* should grab coordinates first and then by pass it to preload gsb*/ std::cout << "By pass here" << std::endl; // read_gsb_unique_blocks(); } From 9c67950a752ffa5cd8a5939c1c32dd484313a3c1 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 7 Aug 2024 03:20:45 -0700 Subject: [PATCH 06/50] preload functions --- openfpga/src/annotation/device_rr_gsb.cpp | 95 +++++++------- openfpga/src/annotation/device_rr_gsb.h | 16 ++- .../src/base/openfpga_build_fabric_template.h | 16 ++- openfpga/src/fabric/read_xml_unique_blocks.h | 120 ++++++++++++------ 4 files changed, 154 insertions(+), 93 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index b3189c055..f0155e339 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -562,58 +562,63 @@ size_t DeviceRRGSB::get_cb_unique_module_index( return cb_unique_module_id; } -void DeviceRRGSB::preload_unique_cbx_module(int x, int y) {} - -void DeviceRRGSB::preload_unique_cby_module(int x, int y) {} - -void DeviceRRGSB::preload_unique_sb_module(int ix, int iy) { - vtr::Point sb_coordinate(ix, iy); - bool is_unique_module = true; - - for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { - /* Check whether the input module exists.*/ - if (sb_unique_module_[id].x() == ix && sb_unique_module_[id].y() == iy) { - is_unique_module = false; - sb_unique_module_id_[ix][iy] = id; +void DeviceRRGSB::preload_unique_cb_module( + const vtr::Point block_coordinate, + const std::vector> instance_coords, + const t_rr_type& cb_type) { + /* Add to list if this is a unique mirror*/ + size_t limit_x; + size_t limit_y; + switch(cb_type){ + case CHANX: + limit_x = cby_unique_module_id_.size(); + limit_y = cby_unique_module_id_[0].size(); break; - } + case CHANY: + limit_x = cby_unique_module_id_.size(); + limit_y = cby_unique_module_id_[0].size(); + break; + default: + VTR_LOG_ERROR("Invalid type"); } - if (true == is_unique_module) { - sb_unique_module_.push_back(sb_coordinate); + + VTR_ASSERT(block_coordinate.x() < limit_x); + VTR_ASSERT(block_coordinate.y() < limit_y); + add_cb_unique_module(cb_type, block_coordinate); + /* Record the id of unique mirror */ + set_cb_unique_module_id(cb_type, block_coordinate, + get_num_cb_unique_module(cb_type) - 1); + + /* Traverse the unique_mirror list and set up its module id */ + for (auto instance_location : instance_coords) { /* Record the id of unique mirror */ - sb_unique_module_id_[ix][iy] = sb_unique_module_.size() - 1; + VTR_ASSERT(instance_location.x() < limit_x); + VTR_ASSERT(instance_location.y() < limit_y); + set_cb_unique_module_id( + cb_type, instance_location, + cbx_unique_module_id_[block_coordinate.x()][block_coordinate.y()]); } } -/* need to preload after cb and sb are preloaded */ -void DeviceRRGSB::preload_unique_gsb_module(int ix, int iy) { - // vtr::Point gsb_coordinate(ix, iy); - // bool is_unique_module = true; +void DeviceRRGSB::preload_unique_sb_module( + const vtr::Point block_coordinate, + const std::vector> instance_coords) { + /*input block coordinate should be within gsb coord range*/ + VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size()); + VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size()); + sb_unique_module_.push_back(block_coordinate); + /* Record the id of unique module */ + sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()] = + sb_unique_module_.size() - 1; - // for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { - // const vtr::Point& gsb_unique_module_coordinate = - // gsb_unique_module_[id]; - // if ((sb_unique_module_id_[ix][iy] == - // sb_unique_module_id_[gsb_unique_module_coordinate.x()] - // [gsb_unique_module_coordinate.y()]) && - // (cbx_unique_module_id_[ix][iy] == - // cbx_unique_module_id_[gsb_unique_module_coordinate.x()] - // [gsb_unique_module_coordinate.y()]) && - // (cby_unique_module_id_[ix][iy] == - // cby_unique_module_id_[gsb_unique_module_coordinate.x()] - // [gsb_unique_module_coordinate.y()])) { - // /* This is a mirror, raise the flag and we finish */ - // is_unique_module = false; - // /* Record the id of unique mirror */ - // gsb_unique_module_id_[ix][iy] = id; - // break; - // } - // } - // if (true == is_unique_module) { - // add_gsb_unique_module(gsb_coordinate); - // /* Record the id of unique mirror */ - // gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1; - // } + /* each mirror instance of the unique module will have the same module id as + * the unique module */ + for (auto instance_location : instance_coords) { + VTR_ASSERT(instance_location.x() < sb_unique_module_id_.size()); + VTR_ASSERT(instance_location.y() < sb_unique_module_id_[0].size()); + sb_unique_module_id_[instance_location.x()][instance_location.y()] = + sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()]; + } } } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 911ed31c4..b6928e91f 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -95,12 +95,16 @@ class DeviceRRGSB { automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ - void preload_unique_cbx_module(int x, int y); - void preload_unique_cby_module(int x, int y); - void preload_unique_sb_module(int x, int y); - void preload_unique_gsb_module(int x, int y); - private: /* Internal cleaners */ - void clear_gsb(); /* clean the content */ + void preload_unique_cb_module( + const vtr::Point block_coordinate, + const std::vector> instance_coords, + const t_rr_type& cb_type); + void preload_unique_sb_module( + const vtr::Point block_coordinate, + const std::vector> instance_coords); + + private: /* Internal cleaners */ + void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ void clear_cb_unique_module_id( const t_rr_type& cb_type); /* clean the content */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 3ba3c1d1a..7566e7d7f 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -20,12 +20,12 @@ #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" +#include "read_xml_unique_blocks.h" #include "rename_modules.h" #include "vtr_log.h" #include "vtr_time.h" #include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" -#include "read_xml_unique_blocks.h" /* begin namespace openfpga */ namespace openfpga { @@ -490,8 +490,13 @@ int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_name = cmd_context.option_value(cmd, opt_file); std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write hierarchy to a file */ - return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), - cmd_context.option_enable(cmd, opt_verbose)); + if (file_type == "xml") { + return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), + file_type.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); + } else { + VTR_LOG_ERROR("file type %s not supported", file_type); + } } template @@ -512,8 +517,9 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write hierarchy to a file */ - return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), - cmd_context.option_enable(cmd, opt_verbose)); + return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), + file_type.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); } } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index b9b17ce91..32cb65d8d 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -23,61 +23,92 @@ /* Headers from libarchfpga */ #include "arch_error.h" +#include "device_rr_gsb_utils.h" #include "read_xml_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" -/******************************************************************** - * Function declaration - *******************************************************************/ -template -int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, - const char* file_type, bool verbose); - /******************************************************************** * Parse XML codes of a to an object of unique_blocks *******************************************************************/ -template -void read_xml_unique_instance_info(T& device_rr_gsb, - pugi::xml_node& xml_instance_info, - const pugiutil::loc_data& loc_data, - std::string type) { +vtr::Point read_xml_unique_instance_info( + pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); - if (type == "sb") { - device_rr_gsb.preload_unique_sb_module(instance_x, instance_y); - } else if (type == "cb") { - // read_cb_unique_blocks(); - std::cout << "By pass here" << std::endl; - } else if (type == "gsb") { - /* should grab coordinates first and then by pass it to preload gsb*/ - std::cout << "By pass here" << std::endl; - // read_gsb_unique_blocks(); - } + vtr::Point instance_coordinate(instance_x, instance_y); + return instance_coordinate; } +template +void report_unique_module_status(T& openfpga_ctx, bool verbose_output) { + /* Report the stats */ + VTR_LOGV( + verbose_output, + "Detected %lu unique X-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX), + find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX), + 100. * + ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), + CHANX) / + (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - + 1.)); + + VTR_LOGV( + verbose_output, + "Detected %lu unique Y-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY), + find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY), + 100. * + ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), + CHANY) / + (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - + 1.)); + + VTR_LOGV( + verbose_output, + "Detected %lu unique switch blocks from a total of %d (compression " + "rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(), + find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(), + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_sb_modules( + openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / + (float)openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - + 1.)); + + VTR_LOG( + "Detected %lu unique general switch blocks from a total of %d " + "(compression " + "rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(), + find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb(), + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_gsb_modules( + openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / + (float)openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - + 1.)); +} /******************************************************************** * Parse XML codes about to an object of *RepackDesignConstraints *******************************************************************/ template int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, - const char* file_type, bool verbose) { + const char* file_type, bool verbose_output) { vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); - - // RepackDesignConstraints repack_design_constraints; - /* Parse the file */ pugi::xml_document doc; pugiutil::loc_data loc_data; - + VTR_ASSERT(strcmp(file_type, "xml") == 0); try { loc_data = pugiutil::load_xml(doc, file_name); pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); /* get device_rr_gsb data type and initialize it*/ - auto device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); + openfpga::DeviceRRGSB& device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); device_rr_gsb.clear(); /* load unique blocks xml file and set up device_rr_gdb */ @@ -86,23 +117,38 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, if (xml_block_info.name() == std::string("block")) { std::string type = get_attribute(xml_block_info, "type", loc_data).as_string(); - std::string block_x = - get_attribute(xml_block_info, "x", loc_data).as_string(); - std::string block_y = - get_attribute(xml_block_info, "y", loc_data).as_string(); + int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); + int block_y = get_attribute(xml_block_info, "y", loc_data).as_int(); + vtr::Point block_coordinate(block_x, block_y); + std::vector> instance_coords; for (pugi::xml_node xml_instance_info : xml_block_info.children()) { if (xml_instance_info.name() == std::string("instance")) { - read_xml_unique_instance_info(device_rr_gsb, xml_instance_info, - loc_data, type); + auto instance_coordinate = + read_xml_unique_instance_info(xml_instance_info, loc_data); + instance_coords.push_back(instance_coordinate); } - // read_xml_unique_instance_info(xml_instance_info, loc_data); + } + /* get block coordinate and instance coordinate, try to setup device rr + * gsb */ + if (type == "sb") { + device_rr_gsb.preload_unique_sb_module(block_coordinate, + instance_coords); + } else if (type == "cby") { + device_rr_gsb.preload_unique_cb_module(block_coordinate, + instance_coords, CHANY); + } else if (type == "cbx") { + device_rr_gsb.preload_unique_cb_module(block_coordinate, + instance_coords, CHANX); + } else { + VTR_LOG_ERROR("Unexpected type!"); } } else { bad_tag(xml_block_info, loc_data, xml_root, {"block"}); return 1; } - // std::cout << "what is the root name: " << xml_block_info.name() << - // std::endl; + } + if (verbose_output) { + report_unique_module_status(openfpga_ctx, true); } } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); From e45619b22d56dc1d4afdc923a6c514ece32c1139 Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 8 Aug 2024 01:00:35 -0700 Subject: [PATCH 07/50] write sb --- openfpga/src/annotation/device_rr_gsb.cpp | 24 +++++- openfpga/src/annotation/device_rr_gsb.h | 5 ++ .../src/base/openfpga_build_fabric_template.h | 3 +- openfpga/src/fabric/read_xml_unique_blocks.h | 73 ++++++++++++++++++- 4 files changed, 100 insertions(+), 5 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index f0155e339..6af394bba 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -569,7 +569,7 @@ void DeviceRRGSB::preload_unique_cb_module( /* Add to list if this is a unique mirror*/ size_t limit_x; size_t limit_y; - switch(cb_type){ + switch (cb_type) { case CHANX: limit_x = cby_unique_module_id_.size(); limit_y = cby_unique_module_id_[0].size(); @@ -621,4 +621,26 @@ void DeviceRRGSB::preload_unique_sb_module( } } +void DeviceRRGSB::get_id_unique_block_map( + std::map>& id_unique_block_map) const { + for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { + const auto& unique_block_coord = sb_unique_module_[id]; + auto unique_module_id = + sb_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + id_unique_block_map[unique_module_id] = unique_block_coord; + } +} + +void DeviceRRGSB::get_id_instance_map( + std::map>>& id_instance_map) const { + for (size_t location_x = 0; location_x < sb_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < sb_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id = sb_unique_module_id_[location_x][location_y]; + vtr::Point instance_coord(location_x, location_y); + id_instance_map[unique_module_id].push_back(instance_coord); + } + } +} } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index b6928e91f..874c08c0e 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -103,6 +103,11 @@ class DeviceRRGSB { const vtr::Point block_coordinate, const std::vector> instance_coords); + void get_id_instance_map( + std::map>>& id_instance_map) const; + void get_id_unique_block_map( + std::map>& id_unique_block_map) const; + private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 7566e7d7f..0e16efc74 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -517,11 +517,10 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write hierarchy to a file */ - return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), + return write_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } - } /* end namespace openfpga */ #endif diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index 32cb65d8d..59ba8d106 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -27,6 +27,8 @@ #include "read_xml_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" +#include "write_xml_utils.h" +#include "openfpga_digest.h" /******************************************************************** * Parse XML codes of a to an object of unique_blocks @@ -135,10 +137,10 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, instance_coords); } else if (type == "cby") { device_rr_gsb.preload_unique_cb_module(block_coordinate, - instance_coords, CHANY); + instance_coords, CHANY); } else if (type == "cbx") { device_rr_gsb.preload_unique_cb_module(block_coordinate, - instance_coords, CHANX); + instance_coords, CHANX); } else { VTR_LOG_ERROR("Unexpected type!"); } @@ -157,4 +159,71 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, return 0; } + +template +int write_xml_sb_blocks(std::fstream& fp, const T& openfpga_ctx) { + std::map> id_unique_block_map; + std::map>> id_instance_map; + openfpga_ctx.device_rr_gsb().get_id_unique_block_map(id_unique_block_map); + openfpga_ctx.device_rr_gsb().get_id_instance_map(id_instance_map); + + /* Validate the file stream */ + if (false == openfpga::valid_file_stream(fp)) { + return 2; + } + for (const auto& pair : id_unique_block_map) { + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + + for (const auto& instance_info : id_instance_map[pair.first]) { + openfpga::write_tab_to_file(fp, 2); + fp << "" + << "\n"; + } + } + + return 0; +} + +template +int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, + const char* file_type, bool verbose_output) { + vtr::ScopedStartFinishTimer timer("Write unique blocks..."); + + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the root node */ + fp << "" + << "\n"; + + int err_code = 0; + + err_code += write_xml_sb_blocks(fp, openfpga_ctx); + + /* Finish writing the root node */ + fp << "" + << "\n"; + + /* Close the file stream */ + fp.close(); + + return err_code; +} + #endif From 755959a890f7d155e9001204e668375099a797b9 Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 8 Aug 2024 02:54:02 -0700 Subject: [PATCH 08/50] add cb cx write function --- openfpga/src/annotation/device_rr_gsb.cpp | 51 +++++++++++++++++++- openfpga/src/annotation/device_rr_gsb.h | 12 ++++- openfpga/src/fabric/read_xml_unique_blocks.h | 48 +++++++++++------- 3 files changed, 90 insertions(+), 21 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 6af394bba..50e1cab33 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -621,7 +621,7 @@ void DeviceRRGSB::preload_unique_sb_module( } } -void DeviceRRGSB::get_id_unique_block_map( +void DeviceRRGSB::get_id_unique_sb_block_map( std::map>& id_unique_block_map) const { for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { const auto& unique_block_coord = sb_unique_module_[id]; @@ -631,7 +631,7 @@ void DeviceRRGSB::get_id_unique_block_map( } } -void DeviceRRGSB::get_id_instance_map( +void DeviceRRGSB::get_id_sb_instance_map( std::map>>& id_instance_map) const { for (size_t location_x = 0; location_x < sb_unique_module_id_.size(); ++location_x) { @@ -643,4 +643,51 @@ void DeviceRRGSB::get_id_instance_map( } } } + +void DeviceRRGSB::get_id_unique_cbx_block_map( + std::map>& id_unique_block_map) const { + for (size_t id = 0; id < get_num_cb_unique_module(CHANX); ++id) { + const auto& unique_block_coord = cbx_unique_module_[id]; + auto unique_module_id = + cbx_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + id_unique_block_map[unique_module_id] = unique_block_coord; + } +} + +void DeviceRRGSB::get_id_cbx_instance_map( + std::map>>& id_instance_map) const { + for (size_t location_x = 0; location_x < cbx_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < cbx_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id = cbx_unique_module_id_[location_x][location_y]; + vtr::Point instance_coord(location_x, location_y); + id_instance_map[unique_module_id].push_back(instance_coord); + } + } +} + +void DeviceRRGSB::get_id_unique_cby_block_map( + std::map>& id_unique_block_map) const { + for (size_t id = 0; id < get_num_cb_unique_module(CHANY); ++id) { + const auto& unique_block_coord = cby_unique_module_[id]; + auto unique_module_id = + cby_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + id_unique_block_map[unique_module_id] = unique_block_coord; + } +} + +void DeviceRRGSB::get_id_cby_instance_map( + std::map>>& id_instance_map) const { + for (size_t location_x = 0; location_x < cby_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < cby_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id = cby_unique_module_id_[location_x][location_y]; + vtr::Point instance_coord(location_x, location_y); + id_instance_map[unique_module_id].push_back(instance_coord); + } + } +} + } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 874c08c0e..513d4b003 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -103,9 +103,17 @@ class DeviceRRGSB { const vtr::Point block_coordinate, const std::vector> instance_coords); - void get_id_instance_map( + void get_id_sb_instance_map( std::map>>& id_instance_map) const; - void get_id_unique_block_map( + void get_id_unique_sb_block_map( + std::map>& id_unique_block_map) const; + void get_id_cbx_instance_map( + std::map>>& id_instance_map) const; + void get_id_unique_cbx_block_map( + std::map>& id_unique_block_map) const; + void get_id_cby_instance_map( + std::map>>& id_instance_map) const; + void get_id_unique_cby_block_map( std::map>& id_unique_block_map) const; private: /* Internal cleaners */ diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index 59ba8d106..395f44afd 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -4,7 +4,7 @@ /******************************************************************** * This file includes the top-level function of this library * which reads an XML of unique routing blocks to the associated - * data structures + * data structures device_rr_gsb *******************************************************************/ #include @@ -24,14 +24,15 @@ /* Headers from libarchfpga */ #include "arch_error.h" #include "device_rr_gsb_utils.h" +#include "openfpga_digest.h" #include "read_xml_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" #include "write_xml_utils.h" -#include "openfpga_digest.h" /******************************************************************** - * Parse XML codes of a to an object of unique_blocks + * Parse XML codes of a to an object of device_rr_gsb + * instance is the mirror module of unique module. *******************************************************************/ vtr::Point read_xml_unique_instance_info( pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { @@ -93,8 +94,7 @@ void report_unique_module_status(T& openfpga_ctx, bool verbose_output) { 1.)); } /******************************************************************** - * Parse XML codes about to an object of - *RepackDesignConstraints + * Parse XML codes about to an object of device_rr_gsb *******************************************************************/ template int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, @@ -159,14 +159,10 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, return 0; } - -template -int write_xml_sb_blocks(std::fstream& fp, const T& openfpga_ctx) { - std::map> id_unique_block_map; - std::map>> id_instance_map; - openfpga_ctx.device_rr_gsb().get_id_unique_block_map(id_unique_block_map); - openfpga_ctx.device_rr_gsb().get_id_instance_map(id_instance_map); - +int write_xml_block( + std::map>& id_unique_block_map, + std::map>>& id_instance_map, + std::fstream& fp, std::string type) { /* Validate the file stream */ if (false == openfpga::valid_file_stream(fp)) { return 2; @@ -174,11 +170,11 @@ int write_xml_sb_blocks(std::fstream& fp, const T& openfpga_ctx) { for (const auto& pair : id_unique_block_map) { openfpga::write_tab_to_file(fp, 1); fp << "" + fp << ">" << "\n"; for (const auto& instance_info : id_instance_map[pair.first]) { @@ -190,6 +186,9 @@ int write_xml_sb_blocks(std::fstream& fp, const T& openfpga_ctx) { fp << "/>" << "\n"; } + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; } return 0; @@ -213,8 +212,23 @@ int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, << "\n"; int err_code = 0; - - err_code += write_xml_sb_blocks(fp, openfpga_ctx); + std::map> id_unique_block_map; + std::map>> id_instance_map; + openfpga_ctx.device_rr_gsb().get_id_unique_sb_block_map(id_unique_block_map); + openfpga_ctx.device_rr_gsb().get_id_sb_instance_map(id_instance_map); + err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "sb"); + + id_unique_block_map.clear(); + id_instance_map.clear(); + openfpga_ctx.device_rr_gsb().get_id_unique_cbx_block_map(id_unique_block_map); + openfpga_ctx.device_rr_gsb().get_id_cbx_instance_map(id_instance_map); + err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cbx"); + + id_unique_block_map.clear(); + id_instance_map.clear(); + openfpga_ctx.device_rr_gsb().get_id_unique_cby_block_map(id_unique_block_map); + openfpga_ctx.device_rr_gsb().get_id_cby_instance_map(id_instance_map); + err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cby"); /* Finish writing the root node */ fp << "" From a785a57520b04f1a2aa1f7387f3a61c7b5b70b0d Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 18 Aug 2024 22:41:40 -0700 Subject: [PATCH 09/50] small bug mod --- openfpga/src/annotation/device_rr_gsb.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 50e1cab33..5831c3638 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -571,8 +571,8 @@ void DeviceRRGSB::preload_unique_cb_module( size_t limit_y; switch (cb_type) { case CHANX: - limit_x = cby_unique_module_id_.size(); - limit_y = cby_unique_module_id_[0].size(); + limit_x = cbx_unique_module_id_.size(); + limit_y = cbx_unique_module_id_[0].size(); break; case CHANY: limit_x = cby_unique_module_id_.size(); From 699131ad58c38007b1425f7a5016d94c80644b02 Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 19 Aug 2024 01:18:06 -0700 Subject: [PATCH 10/50] full flow with bugs --- openfpga/src/annotation/device_rr_gsb.cpp | 19 +++++++++++++------ openfpga/src/annotation/device_rr_gsb.h | 2 +- .../src/base/openfpga_build_fabric_template.h | 12 +++++++++--- .../base/openfpga_setup_command_template.h | 4 ++++ openfpga/src/fabric/read_xml_unique_blocks.h | 3 ++- 5 files changed, 29 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 5831c3638..dc6c2b397 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -421,6 +421,19 @@ void DeviceRRGSB::clear() { clear_sb_unique_module_id(); } +void DeviceRRGSB::clear_unique_modules(){ + /* clean unique module lists */ + clear_cb_unique_module(CHANX); + clear_cb_unique_module_id(CHANX); + + clear_cb_unique_module(CHANY); + clear_cb_unique_module_id(CHANY); + + clear_sb_unique_module(); + clear_sb_unique_module_id(); +} + + void DeviceRRGSB::clear_gsb() { /* clean gsb array */ for (size_t x = 0; x < rr_gsb_.size(); ++x) { @@ -572,18 +585,15 @@ void DeviceRRGSB::preload_unique_cb_module( switch (cb_type) { case CHANX: limit_x = cbx_unique_module_id_.size(); - limit_y = cbx_unique_module_id_[0].size(); break; case CHANY: limit_x = cby_unique_module_id_.size(); - limit_y = cby_unique_module_id_[0].size(); break; default: VTR_LOG_ERROR("Invalid type"); } VTR_ASSERT(block_coordinate.x() < limit_x); - VTR_ASSERT(block_coordinate.y() < limit_y); add_cb_unique_module(cb_type, block_coordinate); /* Record the id of unique mirror */ set_cb_unique_module_id(cb_type, block_coordinate, @@ -593,7 +603,6 @@ void DeviceRRGSB::preload_unique_cb_module( for (auto instance_location : instance_coords) { /* Record the id of unique mirror */ VTR_ASSERT(instance_location.x() < limit_x); - VTR_ASSERT(instance_location.y() < limit_y); set_cb_unique_module_id( cb_type, instance_location, cbx_unique_module_id_[block_coordinate.x()][block_coordinate.y()]); @@ -605,7 +614,6 @@ void DeviceRRGSB::preload_unique_sb_module( const std::vector> instance_coords) { /*input block coordinate should be within gsb coord range*/ VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size()); - VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size()); sb_unique_module_.push_back(block_coordinate); /* Record the id of unique module */ sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()] = @@ -615,7 +623,6 @@ void DeviceRRGSB::preload_unique_sb_module( * the unique module */ for (auto instance_location : instance_coords) { VTR_ASSERT(instance_location.x() < sb_unique_module_id_.size()); - VTR_ASSERT(instance_location.y() < sb_unique_module_id_[0].size()); sb_unique_module_id_[instance_location.x()][instance_location.y()] = sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()]; } diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 513d4b003..699119f63 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -102,7 +102,7 @@ class DeviceRRGSB { void preload_unique_sb_module( const vtr::Point block_coordinate, const std::vector> instance_coords); - + void clear_unique_modules(); void get_id_sb_instance_map( std::map>>& id_instance_map) const; void get_id_unique_sb_block_map( diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 0e16efc74..259e74569 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -101,6 +101,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_frame_view = cmd.option("frame_view"); CommandOptionId opt_compress_routing = cmd.option("compress_routing"); + CommandOptionId opt_preload = cmd.option("preload"); CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); CommandOptionId opt_gen_random_fabric_key = cmd.option("generate_random_fabric_key"); @@ -143,13 +144,18 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, } } - if (true == cmd_context.option_enable(cmd, opt_compress_routing)) { + if (true == cmd_context.option_enable(cmd, opt_compress_routing) && + false == cmd_context.option_enable(cmd, opt_preload)) { compress_routing_hierarchy_template( openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } + if (cmd_context.option_enable(cmd, opt_preload)){ + openfpga_ctx.mutable_flow_manager().set_compress_routing(true); + } + VTR_LOG("\n"); /* Record the execution status in curr_status for each command @@ -518,8 +524,8 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, /* Write hierarchy to a file */ return write_xml_unique_blocks(openfpga_ctx, file_name.c_str(), - file_type.c_str(), - cmd_context.option_enable(cmd, opt_verbose)); + file_type.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 01e2f78cb..9d2631a61 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -391,6 +391,10 @@ ShellCommandId add_build_fabric_command_template( "Compress the number of unique routing modules by " "identifying the unique GSBs"); + /* Add an option '--preload' */ + shell_cmd.add_option("preload", false, + "preload unique routing modules from user input xml file"); + /* Add an option '--duplicate_grid_pin' */ shell_cmd.add_option("duplicate_grid_pin", false, "Duplicate the pins on the same side of a grid"); diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index 395f44afd..e132828de 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -111,7 +111,8 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, /* get device_rr_gsb data type and initialize it*/ openfpga::DeviceRRGSB& device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); - device_rr_gsb.clear(); + /* clear unique modules */ + device_rr_gsb.clear_unique_modules(); /* load unique blocks xml file and set up device_rr_gdb */ for (pugi::xml_node xml_block_info : xml_root.children()) { From 913fdc043ed2f2ef9818c4ae47e35d9db54f1f3e Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 23 Aug 2024 03:52:16 -0700 Subject: [PATCH 11/50] debuged --- openfpga/src/annotation/device_rr_gsb.cpp | 130 +++++++++++++++--- openfpga/src/annotation/device_rr_gsb.h | 22 +-- .../src/base/openfpga_build_fabric_template.h | 5 +- openfpga/src/fabric/read_xml_unique_blocks.h | 35 +++-- 4 files changed, 145 insertions(+), 47 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index dc6c2b397..6acd8bb3f 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -1,8 +1,12 @@ /************************************************************************ * Member functions for class DeviceRRGSB ***********************************************************************/ + #include "device_rr_gsb.h" +#include +#include + #include "rr_gsb_utils.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -182,6 +186,18 @@ void DeviceRRGSB::reserve(const vtr::Point& coordinate) { cby_unique_module_id_[x].resize(coordinate.y()); } } +void DeviceRRGSB::reserve_unique_modules(const vtr::Point& coordinate) { + sb_unique_module_id_.resize(coordinate.x()); + cbx_unique_module_id_.resize(coordinate.x()); + cby_unique_module_id_.resize(coordinate.x()); + + for (size_t x = 0; x < coordinate.x(); ++x) { + sb_unique_module_id_[x].resize(coordinate.y()); + + cbx_unique_module_id_[x].resize(coordinate.y()); + cby_unique_module_id_[x].resize(coordinate.y()); + } +} /* Resize rr_switch_block array is needed*/ void DeviceRRGSB::resize_upon_need(const vtr::Point& coordinate) { @@ -351,7 +367,34 @@ void DeviceRRGSB::build_gsb_unique_module() { } } } - +void DeviceRRGSB::print_txt() { + std::ofstream outFile( + "/home/linear/project/test_data/and2/config/output_read.txt"); + outFile << "################# sb_unique_module_id_ #########" << "\n"; + for (int i = 0; i < sb_unique_module_id_.size(); i++) { + for (int j = 0; j < sb_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << sb_unique_module_id_[i][j] << "\n"; + } + } + outFile << "################# cbx_unique_module_id_ #########" << "\n"; + for (int i = 0; i < cbx_unique_module_id_.size(); i++) { + for (int j = 0; j < cbx_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << cbx_unique_module_id_[i][j] << "\n"; + } + } + outFile << "################# cby_unique_module_id_ #########" << "\n"; + for (int i = 0; i < cby_unique_module_id_.size(); i++) { + for (int j = 0; j < cby_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << cby_unique_module_id_[i][j] << "\n"; + } + } + outFile << "################# gsb_unique_module_id_ #########" << "\n"; + for (int i = 0; i < gsb_unique_module_id_.size(); i++) { + for (int j = 0; j < gsb_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << gsb_unique_module_id_[i][j] << "\n"; + } + } +} void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_sb_unique_module(rr_graph); @@ -359,6 +402,32 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANY); build_gsb_unique_module(); + std::ofstream outFile( + "/home/linear/project/test_data/and2/config/output.txt"); + outFile << "################# sb_unique_module_id_ #########" << "\n"; + for (int i = 0; i < sb_unique_module_id_.size(); i++) { + for (int j = 0; j < sb_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << sb_unique_module_id_[i][j] << "\n"; + } + } + outFile << "################# cbx_unique_module_id_ #########" << "\n"; + for (int i = 0; i < cbx_unique_module_id_.size(); i++) { + for (int j = 0; j < cbx_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << cbx_unique_module_id_[i][j] << "\n"; + } + } + outFile << "################# cby_unique_module_id_ #########" << "\n"; + for (int i = 0; i < cby_unique_module_id_.size(); i++) { + for (int j = 0; j < cby_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << cby_unique_module_id_[i][j] << "\n"; + } + } + outFile << "################# gsb_unique_module_id_ #########" << "\n"; + for (int i = 0; i < gsb_unique_module_id_.size(); i++) { + for (int j = 0; j < gsb_unique_module_id_[0].size(); j++) { + outFile << i << "," << j << ":" << gsb_unique_module_id_[i][j] << "\n"; + } + } } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { @@ -421,7 +490,7 @@ void DeviceRRGSB::clear() { clear_sb_unique_module_id(); } -void DeviceRRGSB::clear_unique_modules(){ +void DeviceRRGSB::clear_unique_modules() { /* clean unique module lists */ clear_cb_unique_module(CHANX); clear_cb_unique_module_id(CHANX); @@ -433,7 +502,6 @@ void DeviceRRGSB::clear_unique_modules(){ clear_sb_unique_module_id(); } - void DeviceRRGSB::clear_gsb() { /* clean gsb array */ for (size_t x = 0; x < rr_gsb_.size(); ++x) { @@ -575,45 +643,62 @@ size_t DeviceRRGSB::get_cb_unique_module_index( return cb_unique_module_id; } -void DeviceRRGSB::preload_unique_cb_module( +void DeviceRRGSB::preload_unique_cbx_module( const vtr::Point block_coordinate, - const std::vector> instance_coords, - const t_rr_type& cb_type) { + const std::vector> instance_coords) { /* Add to list if this is a unique mirror*/ - size_t limit_x; - size_t limit_y; - switch (cb_type) { - case CHANX: - limit_x = cbx_unique_module_id_.size(); - break; - case CHANY: - limit_x = cby_unique_module_id_.size(); - break; - default: - VTR_LOG_ERROR("Invalid type"); - } + size_t limit_x = cbx_unique_module_id_.size(); + size_t limit_y = cbx_unique_module_id_[0].size(); VTR_ASSERT(block_coordinate.x() < limit_x); - add_cb_unique_module(cb_type, block_coordinate); + VTR_ASSERT(block_coordinate.y() < limit_y); + add_cb_unique_module(CHANX, block_coordinate); /* Record the id of unique mirror */ - set_cb_unique_module_id(cb_type, block_coordinate, - get_num_cb_unique_module(cb_type) - 1); + set_cb_unique_module_id(CHANX, block_coordinate, + get_num_cb_unique_module(CHANX) - 1); /* Traverse the unique_mirror list and set up its module id */ for (auto instance_location : instance_coords) { /* Record the id of unique mirror */ VTR_ASSERT(instance_location.x() < limit_x); + VTR_ASSERT(instance_location.y() < limit_y); set_cb_unique_module_id( - cb_type, instance_location, + CHANX, instance_location, cbx_unique_module_id_[block_coordinate.x()][block_coordinate.y()]); } } +void DeviceRRGSB::preload_unique_cby_module( + const vtr::Point block_coordinate, + const std::vector> instance_coords) { + /* Add to list if this is a unique mirror*/ + size_t limit_x = cby_unique_module_id_.size(); + size_t limit_y = cby_unique_module_id_[0].size(); + + VTR_ASSERT(block_coordinate.x() < limit_x); + VTR_ASSERT(block_coordinate.y() < limit_y); + add_cb_unique_module(CHANY, block_coordinate); + /* Record the id of unique mirror */ + set_cb_unique_module_id(CHANY, block_coordinate, + get_num_cb_unique_module(CHANY) - 1); + + /* Traverse the unique_mirror list and set up its module id */ + for (auto instance_location : instance_coords) { + /* Record the id of unique mirror */ + VTR_ASSERT(instance_location.x() < limit_x); + VTR_ASSERT(instance_location.y() < limit_y); + set_cb_unique_module_id( + CHANY, instance_location, + cby_unique_module_id_[block_coordinate.x()][block_coordinate.y()]); + } +} + void DeviceRRGSB::preload_unique_sb_module( const vtr::Point block_coordinate, const std::vector> instance_coords) { /*input block coordinate should be within gsb coord range*/ VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size()); + VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size()); sb_unique_module_.push_back(block_coordinate); /* Record the id of unique module */ sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()] = @@ -623,6 +708,7 @@ void DeviceRRGSB::preload_unique_sb_module( * the unique module */ for (auto instance_location : instance_coords) { VTR_ASSERT(instance_location.x() < sb_unique_module_id_.size()); + VTR_ASSERT(instance_location.y() < sb_unique_module_id_[0].size()); sb_unique_module_id_[instance_location.x()][instance_location.y()] = sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()]; } diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 699119f63..92e0f72d5 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -68,11 +68,14 @@ class DeviceRRGSB { size_t get_cb_unique_module_index(const t_rr_type& cb_type, const vtr::Point& coordinate) const; - public: /* Mutators */ + public: /* Mutators */ + void build_gsb_unique_module(); /* Add a switch block to the array, which will + automatically identify and update the lists + of unique mirrors and rotatable mirrors */ void reserve( const vtr::Point& coordinate); /* Pre-allocate the rr_switch_block array that the device requires */ - void reserve_sb_unique_submodule_id( + void reserve_unique_modules( const vtr::Point& coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ @@ -95,10 +98,13 @@ class DeviceRRGSB { automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ - void preload_unique_cb_module( + void print_txt(); + void preload_unique_cbx_module( const vtr::Point block_coordinate, - const std::vector> instance_coords, - const t_rr_type& cb_type); + const std::vector> instance_coords); + void preload_unique_cby_module( + const vtr::Point block_coordinate, + const std::vector> instance_coords); void preload_unique_sb_module( const vtr::Point block_coordinate, const std::vector> instance_coords); @@ -154,10 +160,8 @@ class DeviceRRGSB { const t_rr_type& cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ - void build_gsb_unique_module(); /* Add a switch block to the array, which will - automatically identify and update the lists - of unique mirrors and rotatable mirrors */ - private: /* Internal Data */ + + private: /* Internal Data */ std::vector> rr_gsb_; std::vector> diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 259e74569..d36a9312b 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -150,9 +150,8 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); - } - - if (cmd_context.option_enable(cmd, opt_preload)){ + } else if (true == cmd_context.option_enable(cmd, opt_compress_routing) && + true == cmd_context.option_enable(cmd, opt_preload)){ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index e132828de..cb021d1a3 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -32,7 +32,7 @@ /******************************************************************** * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror module of unique module. + * instance is the mirror module of unique module. *******************************************************************/ vtr::Point read_xml_unique_instance_info( pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { @@ -113,7 +113,9 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, openfpga::DeviceRRGSB& device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); /* clear unique modules */ device_rr_gsb.clear_unique_modules(); - + vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, + g_vpr_ctx.device().grid.height() - 1); + device_rr_gsb.reserve_unique_modules(grid_coord); /* load unique blocks xml file and set up device_rr_gdb */ for (pugi::xml_node xml_block_info : xml_root.children()) { /* Error out if the XML child has an invalid name! */ @@ -137,11 +139,11 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, device_rr_gsb.preload_unique_sb_module(block_coordinate, instance_coords); } else if (type == "cby") { - device_rr_gsb.preload_unique_cb_module(block_coordinate, - instance_coords, CHANY); + device_rr_gsb.preload_unique_cby_module(block_coordinate, + instance_coords); } else if (type == "cbx") { - device_rr_gsb.preload_unique_cb_module(block_coordinate, - instance_coords, CHANX); + device_rr_gsb.preload_unique_cbx_module(block_coordinate, + instance_coords); } else { VTR_LOG_ERROR("Unexpected type!"); } @@ -150,13 +152,15 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, return 1; } } + device_rr_gsb.build_gsb_unique_module(); + device_rr_gsb.print_txt(); if (verbose_output) { report_unique_module_status(openfpga_ctx, true); } } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); } - + return 0; } @@ -179,13 +183,18 @@ int write_xml_block( << "\n"; for (const auto& instance_info : id_instance_map[pair.first]) { - openfpga::write_tab_to_file(fp, 2); - fp << "" - << "\n"; + fp << "/>" + << "\n"; + } } openfpga::write_tab_to_file(fp, 1); fp << "" From 968824c2dd4701a9a9d2bc7d35a782b9f84a20b8 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 25 Aug 2024 19:56:23 -0700 Subject: [PATCH 12/50] build unique blocks final version --- openfpga/src/annotation/device_rr_gsb.cpp | 55 +----------- openfpga/src/annotation/device_rr_gsb.h | 1 - .../src/base/openfpga_build_fabric_template.h | 4 +- .../base/openfpga_setup_command_template.h | 4 +- ...locks.h => read_write_xml_unique_blocks.h} | 87 ++++++++++++++----- 5 files changed, 72 insertions(+), 79 deletions(-) rename openfpga/src/fabric/{read_xml_unique_blocks.h => read_write_xml_unique_blocks.h} (78%) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 6acd8bb3f..9bd558e16 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -367,34 +367,7 @@ void DeviceRRGSB::build_gsb_unique_module() { } } } -void DeviceRRGSB::print_txt() { - std::ofstream outFile( - "/home/linear/project/test_data/and2/config/output_read.txt"); - outFile << "################# sb_unique_module_id_ #########" << "\n"; - for (int i = 0; i < sb_unique_module_id_.size(); i++) { - for (int j = 0; j < sb_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << sb_unique_module_id_[i][j] << "\n"; - } - } - outFile << "################# cbx_unique_module_id_ #########" << "\n"; - for (int i = 0; i < cbx_unique_module_id_.size(); i++) { - for (int j = 0; j < cbx_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << cbx_unique_module_id_[i][j] << "\n"; - } - } - outFile << "################# cby_unique_module_id_ #########" << "\n"; - for (int i = 0; i < cby_unique_module_id_.size(); i++) { - for (int j = 0; j < cby_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << cby_unique_module_id_[i][j] << "\n"; - } - } - outFile << "################# gsb_unique_module_id_ #########" << "\n"; - for (int i = 0; i < gsb_unique_module_id_.size(); i++) { - for (int j = 0; j < gsb_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << gsb_unique_module_id_[i][j] << "\n"; - } - } -} + void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_sb_unique_module(rr_graph); @@ -402,32 +375,6 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANY); build_gsb_unique_module(); - std::ofstream outFile( - "/home/linear/project/test_data/and2/config/output.txt"); - outFile << "################# sb_unique_module_id_ #########" << "\n"; - for (int i = 0; i < sb_unique_module_id_.size(); i++) { - for (int j = 0; j < sb_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << sb_unique_module_id_[i][j] << "\n"; - } - } - outFile << "################# cbx_unique_module_id_ #########" << "\n"; - for (int i = 0; i < cbx_unique_module_id_.size(); i++) { - for (int j = 0; j < cbx_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << cbx_unique_module_id_[i][j] << "\n"; - } - } - outFile << "################# cby_unique_module_id_ #########" << "\n"; - for (int i = 0; i < cby_unique_module_id_.size(); i++) { - for (int j = 0; j < cby_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << cby_unique_module_id_[i][j] << "\n"; - } - } - outFile << "################# gsb_unique_module_id_ #########" << "\n"; - for (int i = 0; i < gsb_unique_module_id_.size(); i++) { - for (int j = 0; j < gsb_unique_module_id_[0].size(); j++) { - outFile << i << "," << j << ":" << gsb_unique_module_id_[i][j] << "\n"; - } - } } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 92e0f72d5..62dd2c7f0 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -98,7 +98,6 @@ class DeviceRRGSB { automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ - void print_txt(); void preload_unique_cbx_module( const vtr::Point block_coordinate, const std::vector> instance_coords); diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index d36a9312b..357b70288 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -20,7 +20,7 @@ #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" -#include "read_xml_unique_blocks.h" +#include "read_write_xml_unique_blocks.h" #include "rename_modules.h" #include "vtr_log.h" #include "vtr_time.h" @@ -101,7 +101,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_frame_view = cmd.option("frame_view"); CommandOptionId opt_compress_routing = cmd.option("compress_routing"); - CommandOptionId opt_preload = cmd.option("preload"); + CommandOptionId opt_preload = cmd.option("preload_unique_blocks"); CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); CommandOptionId opt_gen_random_fabric_key = cmd.option("generate_random_fabric_key"); diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 9d2631a61..7dcc42338 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -391,8 +391,8 @@ ShellCommandId add_build_fabric_command_template( "Compress the number of unique routing modules by " "identifying the unique GSBs"); - /* Add an option '--preload' */ - shell_cmd.add_option("preload", false, + /* Add an option '--preload_unique_blocks' */ + shell_cmd.add_option("preload_unique_blocks", false, "preload unique routing modules from user input xml file"); /* Add an option '--duplicate_grid_pin' */ diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_write_xml_unique_blocks.h similarity index 78% rename from openfpga/src/fabric/read_xml_unique_blocks.h rename to openfpga/src/fabric/read_write_xml_unique_blocks.h index cb021d1a3..e3ab6cb90 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_write_xml_unique_blocks.h @@ -1,5 +1,5 @@ -#ifndef READ_XML_UNIQUE_BLOCKS_H -#define READ_XML_UNIQUE_BLOCKS_H +#ifndef READ_WRITE_XML_UNIQUE_BLOCKS_H +#define READ_WRITE_XML_UNIQUE_BLOCKS_H /******************************************************************** * This file includes the top-level function of this library @@ -25,7 +25,7 @@ #include "arch_error.h" #include "device_rr_gsb_utils.h" #include "openfpga_digest.h" -#include "read_xml_unique_blocks.h" +#include "read_write_xml_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" #include "write_xml_utils.h" @@ -43,23 +43,16 @@ vtr::Point read_xml_unique_instance_info( } template -void report_unique_module_status(T& openfpga_ctx, bool verbose_output) { +void report_unique_module_status_read(T& openfpga_ctx, bool verbose_output) { /* Report the stats */ VTR_LOGV( verbose_output, - "Detected %lu unique X-direction connection blocks from a total of %d " - "(compression rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX), - find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX), - 100. * - ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), - CHANX) / - (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - - 1.)); + "Read %lu unique X-direction connection blocks ", + openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX)); VTR_LOGV( verbose_output, - "Detected %lu unique Y-direction connection blocks from a total of %d " + "Read %lu unique Y-direction connection blocks from a total of %d " "(compression rate=%.2f%)\n", openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY), find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY), @@ -71,7 +64,7 @@ void report_unique_module_status(T& openfpga_ctx, bool verbose_output) { VTR_LOGV( verbose_output, - "Detected %lu unique switch blocks from a total of %d (compression " + "Read %lu unique switch blocks from a total of %d (compression " "rate=%.2f%)\n", openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(), find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(), @@ -82,7 +75,60 @@ void report_unique_module_status(T& openfpga_ctx, bool verbose_output) { 1.)); VTR_LOG( - "Detected %lu unique general switch blocks from a total of %d " + "Read %lu unique general switch blocks from a total of %d " + "(compression " + "rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(), + find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb(), + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_gsb_modules( + openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / + (float)openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - + 1.)); +} + + +template +void report_unique_module_status_write(T& openfpga_ctx, bool verbose_output) { + /* Report the stats */ + VTR_LOGV( + verbose_output, + "Write %lu unique X-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX), + find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX), + 100. * + ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), + CHANX) / + (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - + 1.)); + + VTR_LOGV( + verbose_output, + "Write %lu unique Y-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY), + find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY), + 100. * + ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), + CHANY) / + (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - + 1.)); + + VTR_LOGV( + verbose_output, + "Write %lu unique switch blocks from a total of %d (compression " + "rate=%.2f%)\n", + openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(), + find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(), + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_sb_modules( + openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / + (float)openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - + 1.)); + + VTR_LOG( + "Write %lu unique general switch blocks from a total of %d " "(compression " "rate=%.2f%)\n", openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(), @@ -153,9 +199,8 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, } } device_rr_gsb.build_gsb_unique_module(); - device_rr_gsb.print_txt(); if (verbose_output) { - report_unique_module_status(openfpga_ctx, true); + report_unique_module_status_read(openfpga_ctx, true); } } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); @@ -208,7 +253,7 @@ template int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, const char* file_type, bool verbose_output) { vtr::ScopedStartFinishTimer timer("Write unique blocks..."); - + VTR_ASSERT(strcmp(file_type, "xml") == 0); /* Create a file handler */ std::fstream fp; /* Open the file stream */ @@ -246,7 +291,9 @@ int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, /* Close the file stream */ fp.close(); - + if (verbose_output) { + report_unique_module_status_write(openfpga_ctx, true); + } return err_code; } From 88fa9f8d39bba660499c17afbb9463a5cac4fbf7 Mon Sep 17 00:00:00 2001 From: Lin Date: Sun, 25 Aug 2024 23:41:19 -0700 Subject: [PATCH 13/50] add test case --- ...read_unique_blocks_example_script.openfpga | 52 +++++++++++++++++++ ...rite_unique_blocks_example_script.openfpga | 49 +++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 4 ++ .../read_unique_blocks/task.config | 35 +++++++++++++ .../write_unique_blocks/task.config | 35 +++++++++++++ 5 files changed, 175 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/task.config diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga new file mode 100644 index 000000000..e73d0039c --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga @@ -0,0 +1,52 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# preload unique blocks from the provided xml file +read_unique_blocks --file ./read_unique_block.xml --verbose –type xml + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --preload_unique_blocks #--verbose + +#write unique blocks xml file +write_unique_blocks --file ./write_unique_block.xml --verbose –type xml + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Write the fabric I/O attributes to a file +# This is used by pin constraint files +write_fabric_io_info --file ./fabric_io_location.xml --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga new file mode 100644 index 000000000..d39105023 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga @@ -0,0 +1,49 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +#write unique blocks xml file +write_unique_blocks --file write_unique_block.xml --verbose –type xml + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Write the fabric I/O attributes to a file +# This is used by pin constraint files +write_fabric_io_info --file ./fabric_io_location.xml --verbose + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index b968904fb..18994424d 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -18,6 +18,10 @@ echo -e "Testing preloading rr_graph" run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ +echo -e "Testing preloading unique blocks" +run-task basic_tests/preload_unique_blocks/write_unique_blocks $@ +run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ + echo -e "Testing testbenches using fpga core wrapper" run-task basic_tests/full_testbench/fpga_core_wrapper $@ run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config new file mode 100644 index 000000000..c8530e603 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/task.config b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/task.config new file mode 100644 index 000000000..2f8171066 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/task.config @@ -0,0 +1,35 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] + From 701a7a5c52ac6ad4d1ef4d26bdbfaa3fb7c26dfe Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 26 Aug 2024 02:45:57 -0700 Subject: [PATCH 14/50] add test case --- ...read_unique_blocks_example_script.openfpga | 4 +- ...rite_unique_blocks_example_script.openfpga | 2 +- .../regression_test_scripts/basic_reg_test.sh | 550 +++++++++--------- .../{task.config => config/task.conf} | 2 +- .../read_unique_blocks/read_unique_block.xml | 22 + .../{task.config => config/task.conf} | 0 .../write_unique_blocks/design_variables.yml | 1 + 7 files changed, 302 insertions(+), 279 deletions(-) rename openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/{task.config => config/task.conf} (91%) create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml rename openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/{task.config => config/task.conf} (100%) create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga index e73d0039c..491cefa4b 100644 --- a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga @@ -16,7 +16,7 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge check_netlist_naming_conflict --fix --report ./netlist_renaming.xml # preload unique blocks from the provided xml file -read_unique_blocks --file ./read_unique_block.xml --verbose –type xml +read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml # Build the module graph # - Enabled compression on routing architecture modules @@ -24,7 +24,7 @@ read_unique_blocks --file ./read_unique_block.xml --verbose –type xml build_fabric --compress_routing --preload_unique_blocks #--verbose #write unique blocks xml file -write_unique_blocks --file ./write_unique_block.xml --verbose –type xml +write_unique_blocks --file ./write_unique_block.xml --verbose --type xml # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows diff --git a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga index d39105023..8df291ccc 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_example_script.openfpga @@ -21,7 +21,7 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml build_fabric --compress_routing #--verbose #write unique blocks xml file -write_unique_blocks --file write_unique_block.xml --verbose –type xml +write_unique_blocks --file ./write_unique_block.xml --verbose --type xml # Write the fabric hierarchy of module graph to a file # This is used by hierarchical PnR flows diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 18994424d..36339d39c 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -5,319 +5,319 @@ source openfpga.sh ############################################### # OpenFPGA Shell with VPR8 ############################################## -echo -e "Basic regression tests"; +# echo -e "Basic regression tests"; -echo -e "Test multiple runs of vpr" -run-task basic_tests/vpr_standalone $@ +# echo -e "Test multiple runs of vpr" +# run-task basic_tests/vpr_standalone $@ -echo -e "Test source commands in openfpga shell" -run-task basic_tests/source_command/source_string $@ -run-task basic_tests/source_command/source_file $@ +# echo -e "Test source commands in openfpga shell" +# run-task basic_tests/source_command/source_string $@ +# run-task basic_tests/source_command/source_file $@ -echo -e "Testing preloading rr_graph" -run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ -run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ +# echo -e "Testing preloading rr_graph" +# run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ +# run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ echo -e "Testing preloading unique blocks" run-task basic_tests/preload_unique_blocks/write_unique_blocks $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ -echo -e "Testing testbenches using fpga core wrapper" -run-task basic_tests/full_testbench/fpga_core_wrapper $@ -run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ -run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ -run-task basic_tests/preconfig_testbench/fpga_core_wrapper $@ -run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules $@ -run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ +# echo -e "Testing testbenches using fpga core wrapper" +# run-task basic_tests/full_testbench/fpga_core_wrapper $@ +# run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ +# run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ +# run-task basic_tests/preconfig_testbench/fpga_core_wrapper $@ +# run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules $@ +# run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ -echo -e "Testing configuration chain of a K4N4 FPGA"; -run-task basic_tests/full_testbench/configuration_chain $@ -run-task basic_tests/full_testbench/configuration_chain_no_time_stamp $@ -run-task basic_tests/full_testbench/configuration_chain_use_reset $@ -run-task basic_tests/full_testbench/configuration_chain_use_resetb $@ -run-task basic_tests/full_testbench/configuration_chain_use_set $@ -run-task basic_tests/full_testbench/configuration_chain_use_setb $@ -run-task basic_tests/full_testbench/configuration_chain_use_set_reset $@ -run-task basic_tests/full_testbench/configuration_chain_config_enable_scff $@ -run-task basic_tests/full_testbench/multi_region_configuration_chain $@ -run-task basic_tests/full_testbench/multi_region_configuration_chain_2clk $@ -run-task basic_tests/full_testbench/multi_region_configuration_chain_3clk $@ -run-task basic_tests/full_testbench/fast_configuration_chain $@ -run-task basic_tests/full_testbench/fast_configuration_chain_use_set $@ -run-task basic_tests/full_testbench/smart_fast_configuration_chain $@ -run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain $@ -run-task basic_tests/preconfig_testbench/configuration_chain $@ -run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io $@ -run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp $@ +# echo -e "Testing configuration chain of a K4N4 FPGA"; +# run-task basic_tests/full_testbench/configuration_chain $@ +# run-task basic_tests/full_testbench/configuration_chain_no_time_stamp $@ +# run-task basic_tests/full_testbench/configuration_chain_use_reset $@ +# run-task basic_tests/full_testbench/configuration_chain_use_resetb $@ +# run-task basic_tests/full_testbench/configuration_chain_use_set $@ +# run-task basic_tests/full_testbench/configuration_chain_use_setb $@ +# run-task basic_tests/full_testbench/configuration_chain_use_set_reset $@ +# run-task basic_tests/full_testbench/configuration_chain_config_enable_scff $@ +# run-task basic_tests/full_testbench/multi_region_configuration_chain $@ +# run-task basic_tests/full_testbench/multi_region_configuration_chain_2clk $@ +# run-task basic_tests/full_testbench/multi_region_configuration_chain_3clk $@ +# run-task basic_tests/full_testbench/fast_configuration_chain $@ +# run-task basic_tests/full_testbench/fast_configuration_chain_use_set $@ +# run-task basic_tests/full_testbench/smart_fast_configuration_chain $@ +# run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain $@ +# run-task basic_tests/preconfig_testbench/configuration_chain $@ +# run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io $@ +# run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp $@ -echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; -run-task basic_tests/full_testbench/configuration_frame $@ -run-task basic_tests/full_testbench/smart_fast_configuration_frame $@ -run-task basic_tests/full_testbench/fast_configuration_frame $@ -run-task basic_tests/full_testbench/fast_configuration_frame_use_set $@ -run-task basic_tests/full_testbench/configuration_frame_ccff $@ -run-task basic_tests/full_testbench/configuration_frame_scff $@ -run-task basic_tests/full_testbench/configuration_frame_use_reset $@ -run-task basic_tests/full_testbench/configuration_frame_use_resetb $@ -run-task basic_tests/full_testbench/configuration_frame_use_set $@ -run-task basic_tests/full_testbench/configuration_frame_use_setb $@ -run-task basic_tests/full_testbench/configuration_frame_use_set_reset $@ -run-task basic_tests/full_testbench/multi_region_configuration_frame $@ -run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame $@ -run-task basic_tests/preconfig_testbench/configuration_frame $@ +# echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; +# run-task basic_tests/full_testbench/configuration_frame $@ +# run-task basic_tests/full_testbench/smart_fast_configuration_frame $@ +# run-task basic_tests/full_testbench/fast_configuration_frame $@ +# run-task basic_tests/full_testbench/fast_configuration_frame_use_set $@ +# run-task basic_tests/full_testbench/configuration_frame_ccff $@ +# run-task basic_tests/full_testbench/configuration_frame_scff $@ +# run-task basic_tests/full_testbench/configuration_frame_use_reset $@ +# run-task basic_tests/full_testbench/configuration_frame_use_resetb $@ +# run-task basic_tests/full_testbench/configuration_frame_use_set $@ +# run-task basic_tests/full_testbench/configuration_frame_use_setb $@ +# run-task basic_tests/full_testbench/configuration_frame_use_set_reset $@ +# run-task basic_tests/full_testbench/multi_region_configuration_frame $@ +# run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame $@ +# run-task basic_tests/preconfig_testbench/configuration_frame $@ -echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; -run-task basic_tests/full_testbench/memory_bank $@ -run-task basic_tests/full_testbench/memory_bank_use_reset $@ -run-task basic_tests/full_testbench/memory_bank_use_resetb $@ -run-task basic_tests/full_testbench/memory_bank_use_set $@ -run-task basic_tests/full_testbench/memory_bank_use_setb $@ -run-task basic_tests/full_testbench/memory_bank_use_set_reset $@ -run-task basic_tests/full_testbench/multi_region_memory_bank $@ -run-task basic_tests/full_testbench/fast_memory_bank $@ -run-task basic_tests/full_testbench/fast_memory_bank_use_set $@ -run-task basic_tests/full_testbench/smart_fast_memory_bank $@ -run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank $@ -run-task basic_tests/preconfig_testbench/memory_bank $@ +# echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; +# run-task basic_tests/full_testbench/memory_bank $@ +# run-task basic_tests/full_testbench/memory_bank_use_reset $@ +# run-task basic_tests/full_testbench/memory_bank_use_resetb $@ +# run-task basic_tests/full_testbench/memory_bank_use_set $@ +# run-task basic_tests/full_testbench/memory_bank_use_setb $@ +# run-task basic_tests/full_testbench/memory_bank_use_set_reset $@ +# run-task basic_tests/full_testbench/multi_region_memory_bank $@ +# run-task basic_tests/full_testbench/fast_memory_bank $@ +# run-task basic_tests/full_testbench/fast_memory_bank_use_set $@ +# run-task basic_tests/full_testbench/smart_fast_memory_bank $@ +# run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank $@ +# run-task basic_tests/preconfig_testbench/memory_bank $@ -echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA"; -run-task basic_tests/full_testbench/ql_memory_bank $@ -run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ -run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ -run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ -run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ -run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ -run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ -run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ -run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@ +# echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA"; +# run-task basic_tests/full_testbench/ql_memory_bank $@ +# run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ +# run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ +# run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ +# run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ +# run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ +# run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ +# run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ +# run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@ -echo -e "Testing simulator support"; -run-task basic_tests/full_testbench/ql_memory_bank_shift_register_vcs $@ +# echo -e "Testing simulator support"; +# run-task basic_tests/full_testbench/ql_memory_bank_shift_register_vcs $@ -echo -e "Testing testbenches without self checking features"; -run-task basic_tests/full_testbench/full_testbench_without_self_checking $@ -run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@ +# echo -e "Testing testbenches without self checking features"; +# run-task basic_tests/full_testbench/full_testbench_without_self_checking $@ +# run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@ -echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; -run-task basic_tests/full_testbench/flatten_memory $@ -run-task basic_tests/preconfig_testbench/flatten_memory $@ +# echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; +# run-task basic_tests/full_testbench/flatten_memory $@ +# run-task basic_tests/preconfig_testbench/flatten_memory $@ -echo -e "Testing fixed device layout and routing channel width"; -run-task basic_tests/fixed_device_support $@ +# echo -e "Testing fixed device layout and routing channel width"; +# run-task basic_tests/fixed_device_support $@ -echo -e "Testing fabric Verilog generation only"; -run-task basic_tests/generate_fabric $@ +# echo -e "Testing fabric Verilog generation only"; +# run-task basic_tests/generate_fabric $@ -echo -e "Testing Verilog testbench generation only"; -run-task basic_tests/generate_testbench $@ -run-task basic_tests/generate_template_testbench $@ +# echo -e "Testing Verilog testbench generation only"; +# run-task basic_tests/generate_testbench $@ +# run-task basic_tests/generate_template_testbench $@ -echo -e "Testing separated Verilog fabric netlists and testbench locations"; -run-task basic_tests/custom_fabric_netlist_location $@ +# echo -e "Testing separated Verilog fabric netlists and testbench locations"; +# run-task basic_tests/custom_fabric_netlist_location $@ -echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@ -run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace $@ -# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank -#run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@ +# echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; +# run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@ +# run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace $@ +# # TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank +# #run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@ -echo -e "Testing Secured FPGA fabrics"; -run-task basic_tests/fabric_key/generate_vanilla_key $@ -run-task basic_tests/fabric_key/generate_multi_region_vanilla_key $@ -run-task basic_tests/fabric_key/generate_random_key $@ -run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@ -run-task basic_tests/fabric_key/load_external_key $@ -run-task basic_tests/fabric_key/load_external_key_cc_fpga $@ -run-task basic_tests/fabric_key/load_external_subkey_cc_fpga $@ -run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@ -run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@ -run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@ -run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga $@ -# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank -#run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga $@ +# echo -e "Testing Secured FPGA fabrics"; +# run-task basic_tests/fabric_key/generate_vanilla_key $@ +# run-task basic_tests/fabric_key/generate_multi_region_vanilla_key $@ +# run-task basic_tests/fabric_key/generate_random_key $@ +# run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@ +# run-task basic_tests/fabric_key/load_external_key $@ +# run-task basic_tests/fabric_key/load_external_key_cc_fpga $@ +# run-task basic_tests/fabric_key/load_external_subkey_cc_fpga $@ +# run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@ +# run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@ +# run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@ +# run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga $@ +# # TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank +# #run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga $@ -echo -e "Testing mock wrapper" -run-task basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping $@ -run-task basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping $@ -run-task basic_tests/mock_wrapper/mock_wrapper_pcf $@ -run-task basic_tests/mock_wrapper/mock_wrapper_bgf $@ +# echo -e "Testing mock wrapper" +# run-task basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping $@ +# run-task basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping $@ +# run-task basic_tests/mock_wrapper/mock_wrapper_pcf $@ +# run-task basic_tests/mock_wrapper/mock_wrapper_bgf $@ -echo -e "Testing K4 series FPGA"; -echo -e "Testing K4N4 with facturable LUTs"; -run-task basic_tests/k4_series/k4n4_frac_lut $@ -echo -e "Testing K4N4 with asynchronous reset"; -run-task basic_tests/k4_series/k4n4_fracff $@ -echo -e "Testing K4N4 with negative edge clocks"; -run-task basic_tests/k4_series/k4n4_fracff2edge $@ -echo -e "Testing K4N4 with hard adders"; -run-task basic_tests/k4_series/k4n4_adder $@ -echo -e "Testing K4N4 without local routing architecture"; -run-task basic_tests/k4_series/k4n4_no_local_routing $@ -echo -e "Testing K4N4 with block RAM"; -run-task basic_tests/k4_series/k4n4_bram $@ -echo -e "Testing K4N4 with LUTRAM"; -run-task basic_tests/k4_series/k4n4_lutram $@ -echo -e "Testing K4N4 with multiple lengths of routing segments"; -run-task basic_tests/k4_series/k4n4_L124 $@ -echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0"; -run-task basic_tests/k4_series/k4n4_chandistr $@ -echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0 and wire segment distribution: x=L124, Y=L12"; -run-task basic_tests/k4_series/k4n4_chandistr_segdist $@ -echo -e "Testing K4N4 with 32-bit fracturable multiplier"; -run-task basic_tests/k4_series/k4n4_frac_mult $@ -echo -e "Testing K4N5 with pattern based local routing"; -run-task basic_tests/k4_series/k4n5_pattern_local_routing $@ -echo -e "Testing K4N4 with custom I/O location syntax"; -run-task basic_tests/k4_series/k4n4_custom_io_loc $@ -run-task basic_tests/k4_series/k4n4_custom_io_loc_center $@ -run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@ -run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ -echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; -run-task basic_tests/k4_series/k4n4_rstOnLut $@ -run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ -echo -e "Testing K4N4 support clock generation by internal resources"; -run-task basic_tests/k4_series/k4n4_clk_gen $@ -echo -e "Testing K4N4 support reset generation by internal resources"; -run-task basic_tests/k4_series/k4n4_rst_gen $@ -echo -e "Testing enhanced connection blocks" -run-task basic_tests/k4_series/k4n4_ecb $@ +# echo -e "Testing K4 series FPGA"; +# echo -e "Testing K4N4 with facturable LUTs"; +# run-task basic_tests/k4_series/k4n4_frac_lut $@ +# echo -e "Testing K4N4 with asynchronous reset"; +# run-task basic_tests/k4_series/k4n4_fracff $@ +# echo -e "Testing K4N4 with negative edge clocks"; +# run-task basic_tests/k4_series/k4n4_fracff2edge $@ +# echo -e "Testing K4N4 with hard adders"; +# run-task basic_tests/k4_series/k4n4_adder $@ +# echo -e "Testing K4N4 without local routing architecture"; +# run-task basic_tests/k4_series/k4n4_no_local_routing $@ +# echo -e "Testing K4N4 with block RAM"; +# run-task basic_tests/k4_series/k4n4_bram $@ +# echo -e "Testing K4N4 with LUTRAM"; +# run-task basic_tests/k4_series/k4n4_lutram $@ +# echo -e "Testing K4N4 with multiple lengths of routing segments"; +# run-task basic_tests/k4_series/k4n4_L124 $@ +# echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0"; +# run-task basic_tests/k4_series/k4n4_chandistr $@ +# echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0 and wire segment distribution: x=L124, Y=L12"; +# run-task basic_tests/k4_series/k4n4_chandistr_segdist $@ +# echo -e "Testing K4N4 with 32-bit fracturable multiplier"; +# run-task basic_tests/k4_series/k4n4_frac_mult $@ +# echo -e "Testing K4N5 with pattern based local routing"; +# run-task basic_tests/k4_series/k4n5_pattern_local_routing $@ +# echo -e "Testing K4N4 with custom I/O location syntax"; +# run-task basic_tests/k4_series/k4n4_custom_io_loc $@ +# run-task basic_tests/k4_series/k4n4_custom_io_loc_center $@ +# run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@ +# run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ +# echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; +# run-task basic_tests/k4_series/k4n4_rstOnLut $@ +# run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ +# echo -e "Testing K4N4 support clock generation by internal resources"; +# run-task basic_tests/k4_series/k4n4_clk_gen $@ +# echo -e "Testing K4N4 support reset generation by internal resources"; +# run-task basic_tests/k4_series/k4n4_rst_gen $@ +# echo -e "Testing enhanced connection blocks" +# run-task basic_tests/k4_series/k4n4_ecb $@ -echo -e "Testing different tile organizations"; -echo -e "Testing tiles with pins only on top and left sides"; -run-task basic_tests/tile_organization/top_left_custom_pins $@ -echo -e "Testing tiles with pins only on top and right sides"; -run-task basic_tests/tile_organization/top_right_custom_pins $@ -echo -e "Testing tiles with pins only on bottom and right sides"; -run-task basic_tests/tile_organization/bottom_right_custom_pins $@ -echo -e "Testing tiles with I/O in center grid"; -run-task basic_tests/tile_organization/tileable_io $@ -echo -e "Testing tiles with I/O consisting of subtiles"; -run-task basic_tests/tile_organization/io_subtile $@ -run-task basic_tests/tile_organization/io_subtile_strong $@ -echo -e "Testing tiles with routing tracks around I/O"; -run-task basic_tests/tile_organization/perimeter_cb $@ -echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; -run-task basic_tests/tile_organization/homo_fabric_tile $@ -run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ -echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; -run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ -run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ -run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@ -run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ -run-task basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile $@ -run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ -run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ -run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ -run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@ -run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@ -run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@ -run-task basic_tests/tile_organization/hetero_fabric_tile $@ -run-task basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig $@ +# echo -e "Testing different tile organizations"; +# echo -e "Testing tiles with pins only on top and left sides"; +# run-task basic_tests/tile_organization/top_left_custom_pins $@ +# echo -e "Testing tiles with pins only on top and right sides"; +# run-task basic_tests/tile_organization/top_right_custom_pins $@ +# echo -e "Testing tiles with pins only on bottom and right sides"; +# run-task basic_tests/tile_organization/bottom_right_custom_pins $@ +# echo -e "Testing tiles with I/O in center grid"; +# run-task basic_tests/tile_organization/tileable_io $@ +# echo -e "Testing tiles with I/O consisting of subtiles"; +# run-task basic_tests/tile_organization/io_subtile $@ +# run-task basic_tests/tile_organization/io_subtile_strong $@ +# echo -e "Testing tiles with routing tracks around I/O"; +# run-task basic_tests/tile_organization/perimeter_cb $@ +# echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; +# run-task basic_tests/tile_organization/homo_fabric_tile $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ +# echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; +# run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +# run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ +# run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@ +# run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ +# run-task basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@ +# run-task basic_tests/tile_organization/hetero_fabric_tile $@ +# run-task basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig $@ -echo -e "Testing group config block"; -run-task basic_tests/group_config_block/group_config_block_homo_full_testbench $@ -run-task basic_tests/group_config_block/group_config_block_homo_Lshape_full_testbench $@ -run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile $@ -run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_Lshape $@ -run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_core_wrapper $@ -run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile $@ -run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape $@ -run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile $@ +# echo -e "Testing group config block"; +# run-task basic_tests/group_config_block/group_config_block_homo_full_testbench $@ +# run-task basic_tests/group_config_block/group_config_block_homo_Lshape_full_testbench $@ +# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile $@ +# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_Lshape $@ +# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_core_wrapper $@ +# run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile $@ +# run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape $@ +# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile $@ -echo -e "Module naming"; -run-task basic_tests/module_naming/using_index $@ -run-task basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index $@ -run-task basic_tests/module_naming/renaming_rules $@ -run-task basic_tests/module_naming/renaming_rules_strong $@ -run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@ +# echo -e "Module naming"; +# run-task basic_tests/module_naming/using_index $@ +# run-task basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index $@ +# run-task basic_tests/module_naming/renaming_rules $@ +# run-task basic_tests/module_naming/renaming_rules_strong $@ +# run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@ -echo -e "Testing global port definition from tiles"; -run-task basic_tests/global_tile_ports/global_tile_clock $@ -run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@ -run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge $@ -run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config $@ -run-task basic_tests/global_tile_ports/global_tile_reset $@ -run-task basic_tests/global_tile_ports/global_tile_4clock --default_tool_path ${OPENFPGA_PATH}/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf $@ -run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ +# echo -e "Testing global port definition from tiles"; +# run-task basic_tests/global_tile_ports/global_tile_clock $@ +# run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@ +# run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge $@ +# run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config $@ +# run-task basic_tests/global_tile_ports/global_tile_reset $@ +# run-task basic_tests/global_tile_ports/global_tile_4clock --default_tool_path ${OPENFPGA_PATH}/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf $@ +# run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ -echo -e "Testing programmable clock architecture"; -run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ -run-task basic_tests/clock_network/homo_1clock_2layer $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_dec $@ -run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ -run-task basic_tests/clock_network/homo_2clock_2layer $@ -run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ -run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ -run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@ -run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ -run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ +# echo -e "Testing programmable clock architecture"; +# run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ +# run-task basic_tests/clock_network/homo_1clock_2layer $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_dec $@ +# run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ +# run-task basic_tests/clock_network/homo_2clock_2layer $@ +# run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ +# run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ +# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ -echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; -run-task basic_tests/verific_test $@ +# echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; +# run-task basic_tests/verific_test $@ -echo -e "Testing explicit multi verilog files"; -run-task basic_tests/explicit_multi_verilog_files $@ +# echo -e "Testing explicit multi verilog files"; +# run-task basic_tests/explicit_multi_verilog_files $@ -echo -e "Test the remove of runtime directories" -clear-task-run basic_tests/explicit_multi_verilog_files $@ +# echo -e "Test the remove of runtime directories" +# clear-task-run basic_tests/explicit_multi_verilog_files $@ -echo -e "Testing write GSB to files"; -run-task basic_tests/write_gsb/write_gsb_to_xml $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_rr_info $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cby $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx_cby $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cbx $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cby $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_include_sb_cbx_cby $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cbx $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cby $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_sb $@ -run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ -run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ -run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ +# echo -e "Testing write GSB to files"; +# run-task basic_tests/write_gsb/write_gsb_to_xml $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_rr_info $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cby $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx_cby $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cbx $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cby $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_include_sb_cbx_cby $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cbx $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cby $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_sb $@ +# run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ +# run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ +# run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ -echo -e "Testing fabric pin physical location file" -run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default $@ -run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ -run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides $@ -run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards $@ +# echo -e "Testing fabric pin physical location file" +# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default $@ +# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ +# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides $@ +# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards $@ -echo -e "Testing bus group features"; -run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ -run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ -run-task basic_tests/bus_group/full_testbench_explicit_mapping $@ -run-task basic_tests/bus_group/full_testbench_implicit_mapping $@ -run-task basic_tests/bus_group/auto_gen_bus_group $@ +# echo -e "Testing bus group features"; +# run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ +# run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ +# run-task basic_tests/bus_group/full_testbench_explicit_mapping $@ +# run-task basic_tests/bus_group/full_testbench_implicit_mapping $@ +# run-task basic_tests/bus_group/auto_gen_bus_group $@ -echo -e "Testing fix pins features"; -run-task basic_tests/io_constraints/fix_pins $@ -run-task basic_tests/io_constraints/example_pcf $@ -run-task basic_tests/io_constraints/empty_pcf $@ -run-task basic_tests/io_constraints/pcf_ql_style $@ +# echo -e "Testing fix pins features"; +# run-task basic_tests/io_constraints/fix_pins $@ +# run-task basic_tests/io_constraints/example_pcf $@ +# run-task basic_tests/io_constraints/empty_pcf $@ +# run-task basic_tests/io_constraints/pcf_ql_style $@ -echo -e "Testing project templates"; -run-task template_tasks/fabric_netlist_gen_template $@ -run-task template_tasks/fabric_verification_template $@ -run-task template_tasks/frac-lut-arch-explore_template $@ -run-task template_tasks/vtr_benchmarks_template $@ +# echo -e "Testing project templates"; +# run-task template_tasks/fabric_netlist_gen_template $@ +# run-task template_tasks/fabric_verification_template $@ +# run-task template_tasks/frac-lut-arch-explore_template $@ +# run-task template_tasks/vtr_benchmarks_template $@ -echo -e "Testing create tsk from template and run task" -create-task _task_copy basic_tests/generate_fabric -run-task _task_copy $@ +# echo -e "Testing create tsk from template and run task" +# create-task _task_copy basic_tests/generate_fabric +# run-task _task_copy $@ -echo -e "Testing output files without time stamp"; -run-task basic_tests/no_time_stamp/device_1x1 $@ -run-task basic_tests/no_time_stamp/device_4x4 $@ -run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ -run-task basic_tests/no_time_stamp/dump_waveform $@ +# echo -e "Testing output files without time stamp"; +# run-task basic_tests/no_time_stamp/device_1x1 $@ +# run-task basic_tests/no_time_stamp/device_4x4 $@ +# run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ +# run-task basic_tests/no_time_stamp/dump_waveform $@ # Run git-diff to ensure no changes on the golden netlists # Switch to root path in case users are running the tests in another location cd ${OPENFPGA_PATH} diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf similarity index 91% rename from openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config rename to openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf index c8530e603..77ec87990 100644 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/task.config +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/config/task.conf @@ -19,7 +19,7 @@ fpga_flow=vpr_blif openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml - +read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml new file mode 100644 index 000000000..0b1fe561c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks/read_unique_block.xml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/task.config b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf similarity index 100% rename from openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/task.config rename to openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml new file mode 100644 index 000000000..de1dbf341 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml @@ -0,0 +1 @@ +TEST_VARIABLE: 100 \ No newline at end of file From 5153cee4ddcbca0104aaa3512a66affae2087fbd Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 26 Aug 2024 02:47:13 -0700 Subject: [PATCH 15/50] mod reg_test script --- .../regression_test_scripts/basic_reg_test.sh | 550 +++++++++--------- 1 file changed, 275 insertions(+), 275 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 36339d39c..18994424d 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -5,319 +5,319 @@ source openfpga.sh ############################################### # OpenFPGA Shell with VPR8 ############################################## -# echo -e "Basic regression tests"; +echo -e "Basic regression tests"; -# echo -e "Test multiple runs of vpr" -# run-task basic_tests/vpr_standalone $@ +echo -e "Test multiple runs of vpr" +run-task basic_tests/vpr_standalone $@ -# echo -e "Test source commands in openfpga shell" -# run-task basic_tests/source_command/source_string $@ -# run-task basic_tests/source_command/source_file $@ +echo -e "Test source commands in openfpga shell" +run-task basic_tests/source_command/source_string $@ +run-task basic_tests/source_command/source_file $@ -# echo -e "Testing preloading rr_graph" -# run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ -# run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ +echo -e "Testing preloading rr_graph" +run-task basic_tests/preload_rr_graph/preload_rr_graph_xml $@ +run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ echo -e "Testing preloading unique blocks" run-task basic_tests/preload_unique_blocks/write_unique_blocks $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ -# echo -e "Testing testbenches using fpga core wrapper" -# run-task basic_tests/full_testbench/fpga_core_wrapper $@ -# run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ -# run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ -# run-task basic_tests/preconfig_testbench/fpga_core_wrapper $@ -# run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules $@ -# run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ +echo -e "Testing testbenches using fpga core wrapper" +run-task basic_tests/full_testbench/fpga_core_wrapper $@ +run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules $@ +run-task basic_tests/full_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ +run-task basic_tests/preconfig_testbench/fpga_core_wrapper $@ +run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules $@ +run-task basic_tests/preconfig_testbench/fpga_core_wrapper_naming_rules_use_core_tb $@ -# echo -e "Testing configuration chain of a K4N4 FPGA"; -# run-task basic_tests/full_testbench/configuration_chain $@ -# run-task basic_tests/full_testbench/configuration_chain_no_time_stamp $@ -# run-task basic_tests/full_testbench/configuration_chain_use_reset $@ -# run-task basic_tests/full_testbench/configuration_chain_use_resetb $@ -# run-task basic_tests/full_testbench/configuration_chain_use_set $@ -# run-task basic_tests/full_testbench/configuration_chain_use_setb $@ -# run-task basic_tests/full_testbench/configuration_chain_use_set_reset $@ -# run-task basic_tests/full_testbench/configuration_chain_config_enable_scff $@ -# run-task basic_tests/full_testbench/multi_region_configuration_chain $@ -# run-task basic_tests/full_testbench/multi_region_configuration_chain_2clk $@ -# run-task basic_tests/full_testbench/multi_region_configuration_chain_3clk $@ -# run-task basic_tests/full_testbench/fast_configuration_chain $@ -# run-task basic_tests/full_testbench/fast_configuration_chain_use_set $@ -# run-task basic_tests/full_testbench/smart_fast_configuration_chain $@ -# run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain $@ -# run-task basic_tests/preconfig_testbench/configuration_chain $@ -# run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io $@ -# run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp $@ +echo -e "Testing configuration chain of a K4N4 FPGA"; +run-task basic_tests/full_testbench/configuration_chain $@ +run-task basic_tests/full_testbench/configuration_chain_no_time_stamp $@ +run-task basic_tests/full_testbench/configuration_chain_use_reset $@ +run-task basic_tests/full_testbench/configuration_chain_use_resetb $@ +run-task basic_tests/full_testbench/configuration_chain_use_set $@ +run-task basic_tests/full_testbench/configuration_chain_use_setb $@ +run-task basic_tests/full_testbench/configuration_chain_use_set_reset $@ +run-task basic_tests/full_testbench/configuration_chain_config_enable_scff $@ +run-task basic_tests/full_testbench/multi_region_configuration_chain $@ +run-task basic_tests/full_testbench/multi_region_configuration_chain_2clk $@ +run-task basic_tests/full_testbench/multi_region_configuration_chain_3clk $@ +run-task basic_tests/full_testbench/fast_configuration_chain $@ +run-task basic_tests/full_testbench/fast_configuration_chain_use_set $@ +run-task basic_tests/full_testbench/smart_fast_configuration_chain $@ +run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain $@ +run-task basic_tests/preconfig_testbench/configuration_chain $@ +run-task basic_tests/preconfig_testbench/configuration_chain_config_done_io $@ +run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp $@ -# echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; -# run-task basic_tests/full_testbench/configuration_frame $@ -# run-task basic_tests/full_testbench/smart_fast_configuration_frame $@ -# run-task basic_tests/full_testbench/fast_configuration_frame $@ -# run-task basic_tests/full_testbench/fast_configuration_frame_use_set $@ -# run-task basic_tests/full_testbench/configuration_frame_ccff $@ -# run-task basic_tests/full_testbench/configuration_frame_scff $@ -# run-task basic_tests/full_testbench/configuration_frame_use_reset $@ -# run-task basic_tests/full_testbench/configuration_frame_use_resetb $@ -# run-task basic_tests/full_testbench/configuration_frame_use_set $@ -# run-task basic_tests/full_testbench/configuration_frame_use_setb $@ -# run-task basic_tests/full_testbench/configuration_frame_use_set_reset $@ -# run-task basic_tests/full_testbench/multi_region_configuration_frame $@ -# run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame $@ -# run-task basic_tests/preconfig_testbench/configuration_frame $@ +echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; +run-task basic_tests/full_testbench/configuration_frame $@ +run-task basic_tests/full_testbench/smart_fast_configuration_frame $@ +run-task basic_tests/full_testbench/fast_configuration_frame $@ +run-task basic_tests/full_testbench/fast_configuration_frame_use_set $@ +run-task basic_tests/full_testbench/configuration_frame_ccff $@ +run-task basic_tests/full_testbench/configuration_frame_scff $@ +run-task basic_tests/full_testbench/configuration_frame_use_reset $@ +run-task basic_tests/full_testbench/configuration_frame_use_resetb $@ +run-task basic_tests/full_testbench/configuration_frame_use_set $@ +run-task basic_tests/full_testbench/configuration_frame_use_setb $@ +run-task basic_tests/full_testbench/configuration_frame_use_set_reset $@ +run-task basic_tests/full_testbench/multi_region_configuration_frame $@ +run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_frame $@ +run-task basic_tests/preconfig_testbench/configuration_frame $@ -# echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; -# run-task basic_tests/full_testbench/memory_bank $@ -# run-task basic_tests/full_testbench/memory_bank_use_reset $@ -# run-task basic_tests/full_testbench/memory_bank_use_resetb $@ -# run-task basic_tests/full_testbench/memory_bank_use_set $@ -# run-task basic_tests/full_testbench/memory_bank_use_setb $@ -# run-task basic_tests/full_testbench/memory_bank_use_set_reset $@ -# run-task basic_tests/full_testbench/multi_region_memory_bank $@ -# run-task basic_tests/full_testbench/fast_memory_bank $@ -# run-task basic_tests/full_testbench/fast_memory_bank_use_set $@ -# run-task basic_tests/full_testbench/smart_fast_memory_bank $@ -# run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank $@ -# run-task basic_tests/preconfig_testbench/memory_bank $@ +echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; +run-task basic_tests/full_testbench/memory_bank $@ +run-task basic_tests/full_testbench/memory_bank_use_reset $@ +run-task basic_tests/full_testbench/memory_bank_use_resetb $@ +run-task basic_tests/full_testbench/memory_bank_use_set $@ +run-task basic_tests/full_testbench/memory_bank_use_setb $@ +run-task basic_tests/full_testbench/memory_bank_use_set_reset $@ +run-task basic_tests/full_testbench/multi_region_memory_bank $@ +run-task basic_tests/full_testbench/fast_memory_bank $@ +run-task basic_tests/full_testbench/fast_memory_bank_use_set $@ +run-task basic_tests/full_testbench/smart_fast_memory_bank $@ +run-task basic_tests/full_testbench/smart_fast_multi_region_memory_bank $@ +run-task basic_tests/preconfig_testbench/memory_bank $@ -# echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA"; -# run-task basic_tests/full_testbench/ql_memory_bank $@ -# run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ -# run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ -# run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ -# run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ -# run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ -# run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ -# run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ -# run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@ +echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA"; +run-task basic_tests/full_testbench/ql_memory_bank $@ +run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ +run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ +run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ +run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ +run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ +run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ +run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ +run-task basic_tests/full_testbench/ql_memory_bank_shift_register_multi_chain $@ -# echo -e "Testing simulator support"; -# run-task basic_tests/full_testbench/ql_memory_bank_shift_register_vcs $@ +echo -e "Testing simulator support"; +run-task basic_tests/full_testbench/ql_memory_bank_shift_register_vcs $@ -# echo -e "Testing testbenches without self checking features"; -# run-task basic_tests/full_testbench/full_testbench_without_self_checking $@ -# run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@ +echo -e "Testing testbenches without self checking features"; +run-task basic_tests/full_testbench/full_testbench_without_self_checking $@ +run-task basic_tests/preconfig_testbench/preconfigured_testbench_without_self_checking $@ -# echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; -# run-task basic_tests/full_testbench/flatten_memory $@ -# run-task basic_tests/preconfig_testbench/flatten_memory $@ +echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; +run-task basic_tests/full_testbench/flatten_memory $@ +run-task basic_tests/preconfig_testbench/flatten_memory $@ -# echo -e "Testing fixed device layout and routing channel width"; -# run-task basic_tests/fixed_device_support $@ +echo -e "Testing fixed device layout and routing channel width"; +run-task basic_tests/fixed_device_support $@ -# echo -e "Testing fabric Verilog generation only"; -# run-task basic_tests/generate_fabric $@ +echo -e "Testing fabric Verilog generation only"; +run-task basic_tests/generate_fabric $@ -# echo -e "Testing Verilog testbench generation only"; -# run-task basic_tests/generate_testbench $@ -# run-task basic_tests/generate_template_testbench $@ +echo -e "Testing Verilog testbench generation only"; +run-task basic_tests/generate_testbench $@ +run-task basic_tests/generate_template_testbench $@ -# echo -e "Testing separated Verilog fabric netlists and testbench locations"; -# run-task basic_tests/custom_fabric_netlist_location $@ +echo -e "Testing separated Verilog fabric netlists and testbench locations"; +run-task basic_tests/custom_fabric_netlist_location $@ -# echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -# run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@ -# run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace $@ -# # TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank -# #run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@ +echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; +run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq $@ +run-task basic_tests/fixed_simulation_settings/fixed_operating_clock_freq_no_ace $@ +# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank +#run-task basic_tests/fixed_simulation_settings/fixed_shift_register_clock_freq $@ -# echo -e "Testing Secured FPGA fabrics"; -# run-task basic_tests/fabric_key/generate_vanilla_key $@ -# run-task basic_tests/fabric_key/generate_multi_region_vanilla_key $@ -# run-task basic_tests/fabric_key/generate_random_key $@ -# run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@ -# run-task basic_tests/fabric_key/load_external_key $@ -# run-task basic_tests/fabric_key/load_external_key_cc_fpga $@ -# run-task basic_tests/fabric_key/load_external_subkey_cc_fpga $@ -# run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@ -# run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@ -# run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@ -# run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga $@ -# # TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank -# #run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga $@ +echo -e "Testing Secured FPGA fabrics"; +run-task basic_tests/fabric_key/generate_vanilla_key $@ +run-task basic_tests/fabric_key/generate_multi_region_vanilla_key $@ +run-task basic_tests/fabric_key/generate_random_key $@ +run-task basic_tests/fabric_key/generate_random_key_ql_memory_bank $@ +run-task basic_tests/fabric_key/load_external_key $@ +run-task basic_tests/fabric_key/load_external_key_cc_fpga $@ +run-task basic_tests/fabric_key/load_external_subkey_cc_fpga $@ +run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga $@ +run-task basic_tests/fabric_key/load_external_key_qlbank_fpga $@ +run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga $@ +run-task basic_tests/fabric_key/load_external_key_qlbanksr_multi_chain_fpga $@ +# TODO: This feature is temporarily out of test due to the emergency in delivering netlists for multi-chain shift-register memory bank +#run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga $@ -# echo -e "Testing mock wrapper" -# run-task basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping $@ -# run-task basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping $@ -# run-task basic_tests/mock_wrapper/mock_wrapper_pcf $@ -# run-task basic_tests/mock_wrapper/mock_wrapper_bgf $@ +echo -e "Testing mock wrapper" +run-task basic_tests/mock_wrapper/mock_wrapper_explicit_port_mapping $@ +run-task basic_tests/mock_wrapper/mock_wrapper_implicit_port_mapping $@ +run-task basic_tests/mock_wrapper/mock_wrapper_pcf $@ +run-task basic_tests/mock_wrapper/mock_wrapper_bgf $@ -# echo -e "Testing K4 series FPGA"; -# echo -e "Testing K4N4 with facturable LUTs"; -# run-task basic_tests/k4_series/k4n4_frac_lut $@ -# echo -e "Testing K4N4 with asynchronous reset"; -# run-task basic_tests/k4_series/k4n4_fracff $@ -# echo -e "Testing K4N4 with negative edge clocks"; -# run-task basic_tests/k4_series/k4n4_fracff2edge $@ -# echo -e "Testing K4N4 with hard adders"; -# run-task basic_tests/k4_series/k4n4_adder $@ -# echo -e "Testing K4N4 without local routing architecture"; -# run-task basic_tests/k4_series/k4n4_no_local_routing $@ -# echo -e "Testing K4N4 with block RAM"; -# run-task basic_tests/k4_series/k4n4_bram $@ -# echo -e "Testing K4N4 with LUTRAM"; -# run-task basic_tests/k4_series/k4n4_lutram $@ -# echo -e "Testing K4N4 with multiple lengths of routing segments"; -# run-task basic_tests/k4_series/k4n4_L124 $@ -# echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0"; -# run-task basic_tests/k4_series/k4n4_chandistr $@ -# echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0 and wire segment distribution: x=L124, Y=L12"; -# run-task basic_tests/k4_series/k4n4_chandistr_segdist $@ -# echo -e "Testing K4N4 with 32-bit fracturable multiplier"; -# run-task basic_tests/k4_series/k4n4_frac_mult $@ -# echo -e "Testing K4N5 with pattern based local routing"; -# run-task basic_tests/k4_series/k4n5_pattern_local_routing $@ -# echo -e "Testing K4N4 with custom I/O location syntax"; -# run-task basic_tests/k4_series/k4n4_custom_io_loc $@ -# run-task basic_tests/k4_series/k4n4_custom_io_loc_center $@ -# run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@ -# run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ -# echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; -# run-task basic_tests/k4_series/k4n4_rstOnLut $@ -# run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ -# echo -e "Testing K4N4 support clock generation by internal resources"; -# run-task basic_tests/k4_series/k4n4_clk_gen $@ -# echo -e "Testing K4N4 support reset generation by internal resources"; -# run-task basic_tests/k4_series/k4n4_rst_gen $@ -# echo -e "Testing enhanced connection blocks" -# run-task basic_tests/k4_series/k4n4_ecb $@ +echo -e "Testing K4 series FPGA"; +echo -e "Testing K4N4 with facturable LUTs"; +run-task basic_tests/k4_series/k4n4_frac_lut $@ +echo -e "Testing K4N4 with asynchronous reset"; +run-task basic_tests/k4_series/k4n4_fracff $@ +echo -e "Testing K4N4 with negative edge clocks"; +run-task basic_tests/k4_series/k4n4_fracff2edge $@ +echo -e "Testing K4N4 with hard adders"; +run-task basic_tests/k4_series/k4n4_adder $@ +echo -e "Testing K4N4 without local routing architecture"; +run-task basic_tests/k4_series/k4n4_no_local_routing $@ +echo -e "Testing K4N4 with block RAM"; +run-task basic_tests/k4_series/k4n4_bram $@ +echo -e "Testing K4N4 with LUTRAM"; +run-task basic_tests/k4_series/k4n4_lutram $@ +echo -e "Testing K4N4 with multiple lengths of routing segments"; +run-task basic_tests/k4_series/k4n4_L124 $@ +echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0"; +run-task basic_tests/k4_series/k4n4_chandistr $@ +echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0 and wire segment distribution: x=L124, Y=L12"; +run-task basic_tests/k4_series/k4n4_chandistr_segdist $@ +echo -e "Testing K4N4 with 32-bit fracturable multiplier"; +run-task basic_tests/k4_series/k4n4_frac_mult $@ +echo -e "Testing K4N5 with pattern based local routing"; +run-task basic_tests/k4_series/k4n5_pattern_local_routing $@ +echo -e "Testing K4N4 with custom I/O location syntax"; +run-task basic_tests/k4_series/k4n4_custom_io_loc $@ +run-task basic_tests/k4_series/k4n4_custom_io_loc_center $@ +run-task basic_tests/k4_series/k4n4_custom_io_loc_center_height_odd $@ +run-task basic_tests/k4_series/k4n4_custom_io_loc_center_width_odd $@ +echo -e "Testing K4N4 with a local routing where reset can driven LUT inputs"; +run-task basic_tests/k4_series/k4n4_rstOnLut $@ +run-task basic_tests/k4_series/k4n4_rstOnLut_strong $@ +echo -e "Testing K4N4 support clock generation by internal resources"; +run-task basic_tests/k4_series/k4n4_clk_gen $@ +echo -e "Testing K4N4 support reset generation by internal resources"; +run-task basic_tests/k4_series/k4n4_rst_gen $@ +echo -e "Testing enhanced connection blocks" +run-task basic_tests/k4_series/k4n4_ecb $@ -# echo -e "Testing different tile organizations"; -# echo -e "Testing tiles with pins only on top and left sides"; -# run-task basic_tests/tile_organization/top_left_custom_pins $@ -# echo -e "Testing tiles with pins only on top and right sides"; -# run-task basic_tests/tile_organization/top_right_custom_pins $@ -# echo -e "Testing tiles with pins only on bottom and right sides"; -# run-task basic_tests/tile_organization/bottom_right_custom_pins $@ -# echo -e "Testing tiles with I/O in center grid"; -# run-task basic_tests/tile_organization/tileable_io $@ -# echo -e "Testing tiles with I/O consisting of subtiles"; -# run-task basic_tests/tile_organization/io_subtile $@ -# run-task basic_tests/tile_organization/io_subtile_strong $@ -# echo -e "Testing tiles with routing tracks around I/O"; -# run-task basic_tests/tile_organization/perimeter_cb $@ -# echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; -# run-task basic_tests/tile_organization/homo_fabric_tile $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ -# echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; -# run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ -# run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ -# run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@ -# run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ -# run-task basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@ -# run-task basic_tests/tile_organization/hetero_fabric_tile $@ -# run-task basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig $@ +echo -e "Testing different tile organizations"; +echo -e "Testing tiles with pins only on top and left sides"; +run-task basic_tests/tile_organization/top_left_custom_pins $@ +echo -e "Testing tiles with pins only on top and right sides"; +run-task basic_tests/tile_organization/top_right_custom_pins $@ +echo -e "Testing tiles with pins only on bottom and right sides"; +run-task basic_tests/tile_organization/bottom_right_custom_pins $@ +echo -e "Testing tiles with I/O in center grid"; +run-task basic_tests/tile_organization/tileable_io $@ +echo -e "Testing tiles with I/O consisting of subtiles"; +run-task basic_tests/tile_organization/io_subtile $@ +run-task basic_tests/tile_organization/io_subtile_strong $@ +echo -e "Testing tiles with routing tracks around I/O"; +run-task basic_tests/tile_organization/perimeter_cb $@ +echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)"; +run-task basic_tests/tile_organization/homo_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_bl $@ +echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)"; +run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@ +run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@ +run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@ +run-task basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@ +run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@ +run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@ +run-task basic_tests/tile_organization/homo_fabric_tile_global_tile_clock $@ +run-task basic_tests/tile_organization/homo_fabric_tile_adder_chain $@ +run-task basic_tests/tile_organization/homo_fabric_tile_clkntwk $@ +run-task basic_tests/tile_organization/hetero_fabric_tile $@ +run-task basic_tests/tile_organization/homo_fabric_tile_ecb_2x2_preconfig $@ -# echo -e "Testing group config block"; -# run-task basic_tests/group_config_block/group_config_block_homo_full_testbench $@ -# run-task basic_tests/group_config_block/group_config_block_homo_Lshape_full_testbench $@ -# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile $@ -# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_Lshape $@ -# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_core_wrapper $@ -# run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile $@ -# run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape $@ -# run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile $@ +echo -e "Testing group config block"; +run-task basic_tests/group_config_block/group_config_block_homo_full_testbench $@ +run-task basic_tests/group_config_block/group_config_block_homo_Lshape_full_testbench $@ +run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile $@ +run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_Lshape $@ +run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_core_wrapper $@ +run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile $@ +run-task basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape $@ +run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile $@ -# echo -e "Module naming"; -# run-task basic_tests/module_naming/using_index $@ -# run-task basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index $@ -# run-task basic_tests/module_naming/renaming_rules $@ -# run-task basic_tests/module_naming/renaming_rules_strong $@ -# run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@ +echo -e "Module naming"; +run-task basic_tests/module_naming/using_index $@ +run-task basic_tests/module_naming/fabric_tile_clkntwk_io_subtile_using_index $@ +run-task basic_tests/module_naming/renaming_rules $@ +run-task basic_tests/module_naming/renaming_rules_strong $@ +run-task basic_tests/module_naming/renaming_rules_on_indexed_names $@ -# echo -e "Testing global port definition from tiles"; -# run-task basic_tests/global_tile_ports/global_tile_clock $@ -# run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@ -# run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge $@ -# run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config $@ -# run-task basic_tests/global_tile_ports/global_tile_reset $@ -# run-task basic_tests/global_tile_ports/global_tile_4clock --default_tool_path ${OPENFPGA_PATH}/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf $@ -# run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ +echo -e "Testing global port definition from tiles"; +run-task basic_tests/global_tile_ports/global_tile_clock $@ +run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@ +run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge $@ +run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config $@ +run-task basic_tests/global_tile_ports/global_tile_reset $@ +run-task basic_tests/global_tile_ports/global_tile_4clock --default_tool_path ${OPENFPGA_PATH}/openfpga_flow/misc/fpgaflow_default_tool_path_timing.conf $@ +run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@ -# echo -e "Testing programmable clock architecture"; -# run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ -# run-task basic_tests/clock_network/homo_1clock_2layer $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_dec $@ -# run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ -# run-task basic_tests/clock_network/homo_2clock_2layer $@ -# run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ -# run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ -# run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ +echo -e "Testing programmable clock architecture"; +run-task basic_tests/clock_network/homo_1clock_1reset_1layer_2entry $@ +run-task basic_tests/clock_network/homo_1clock_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_dec $@ +run-task basic_tests/clock_network/homo_1clock_2layer_full_tb $@ +run-task basic_tests/clock_network/homo_2clock_2layer $@ +run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@ +run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@ +run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@ +run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry_disable_unused $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ -# echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; -# run-task basic_tests/verific_test $@ +echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; +run-task basic_tests/verific_test $@ -# echo -e "Testing explicit multi verilog files"; -# run-task basic_tests/explicit_multi_verilog_files $@ +echo -e "Testing explicit multi verilog files"; +run-task basic_tests/explicit_multi_verilog_files $@ -# echo -e "Test the remove of runtime directories" -# clear-task-run basic_tests/explicit_multi_verilog_files $@ +echo -e "Test the remove of runtime directories" +clear-task-run basic_tests/explicit_multi_verilog_files $@ -# echo -e "Testing write GSB to files"; -# run-task basic_tests/write_gsb/write_gsb_to_xml $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_rr_info $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cby $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx_cby $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cbx $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cby $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_include_sb_cbx_cby $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cbx $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cby $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_sb $@ -# run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ -# run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ -# run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ +echo -e "Testing write GSB to files"; +run-task basic_tests/write_gsb/write_gsb_to_xml $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_rr_info $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cby $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_cbx_cby $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cbx $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_exclude_sb_cby $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_include_sb_cbx_cby $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cbx $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_cby $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_include_single_sb $@ +run-task basic_tests/write_gsb/write_gsb_to_xml_compress_routing $@ +run-task basic_tests/write_gsb/write_unique_gsb_to_xml $@ +run-task basic_tests/write_gsb/write_unique_gsb_to_xml_compress_routing $@ -# echo -e "Testing fabric pin physical location file" -# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default $@ -# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ -# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides $@ -# run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards $@ +echo -e "Testing fabric pin physical location file" +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_default $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_for_tiles $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_show_invalid_sides $@ +run-task basic_tests/write_fabric_pin_phy_loc/write_fabric_pin_phy_loc_wildcards $@ -# echo -e "Testing bus group features"; -# run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ -# run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ -# run-task basic_tests/bus_group/full_testbench_explicit_mapping $@ -# run-task basic_tests/bus_group/full_testbench_implicit_mapping $@ -# run-task basic_tests/bus_group/auto_gen_bus_group $@ +echo -e "Testing bus group features"; +run-task basic_tests/bus_group/preconfig_testbench_explicit_mapping $@ +run-task basic_tests/bus_group/preconfig_testbench_implicit_mapping $@ +run-task basic_tests/bus_group/full_testbench_explicit_mapping $@ +run-task basic_tests/bus_group/full_testbench_implicit_mapping $@ +run-task basic_tests/bus_group/auto_gen_bus_group $@ -# echo -e "Testing fix pins features"; -# run-task basic_tests/io_constraints/fix_pins $@ -# run-task basic_tests/io_constraints/example_pcf $@ -# run-task basic_tests/io_constraints/empty_pcf $@ -# run-task basic_tests/io_constraints/pcf_ql_style $@ +echo -e "Testing fix pins features"; +run-task basic_tests/io_constraints/fix_pins $@ +run-task basic_tests/io_constraints/example_pcf $@ +run-task basic_tests/io_constraints/empty_pcf $@ +run-task basic_tests/io_constraints/pcf_ql_style $@ -# echo -e "Testing project templates"; -# run-task template_tasks/fabric_netlist_gen_template $@ -# run-task template_tasks/fabric_verification_template $@ -# run-task template_tasks/frac-lut-arch-explore_template $@ -# run-task template_tasks/vtr_benchmarks_template $@ +echo -e "Testing project templates"; +run-task template_tasks/fabric_netlist_gen_template $@ +run-task template_tasks/fabric_verification_template $@ +run-task template_tasks/frac-lut-arch-explore_template $@ +run-task template_tasks/vtr_benchmarks_template $@ -# echo -e "Testing create tsk from template and run task" -# create-task _task_copy basic_tests/generate_fabric -# run-task _task_copy $@ +echo -e "Testing create tsk from template and run task" +create-task _task_copy basic_tests/generate_fabric +run-task _task_copy $@ -# echo -e "Testing output files without time stamp"; -# run-task basic_tests/no_time_stamp/device_1x1 $@ -# run-task basic_tests/no_time_stamp/device_4x4 $@ -# run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ -# run-task basic_tests/no_time_stamp/dump_waveform $@ +echo -e "Testing output files without time stamp"; +run-task basic_tests/no_time_stamp/device_1x1 $@ +run-task basic_tests/no_time_stamp/device_4x4 $@ +run-task basic_tests/no_time_stamp/no_cout_in_gsb $@ +run-task basic_tests/no_time_stamp/dump_waveform $@ # Run git-diff to ensure no changes on the golden netlists # Switch to root path in case users are running the tests in another location cd ${OPENFPGA_PATH} From 67c7c2da66afa33836a074deccc53a705e0213c3 Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 26 Aug 2024 03:07:06 -0700 Subject: [PATCH 16/50] mod comments --- openfpga/src/annotation/device_rr_gsb.cpp | 28 ++++++++++--------- .../src/base/openfpga_build_fabric_template.h | 4 +-- .../src/fabric/read_write_xml_unique_blocks.h | 16 ++++++----- 3 files changed, 26 insertions(+), 22 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index ccbda2bbc..0537274e5 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -2,11 +2,9 @@ * Member functions for class DeviceRRGSB ***********************************************************************/ -#include "device_rr_gsb.h" - #include #include - +#include "device_rr_gsb.h" #include "rr_gsb_utils.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -582,20 +580,19 @@ size_t DeviceRRGSB::get_cb_unique_module_index( void DeviceRRGSB::preload_unique_cbx_module( const vtr::Point block_coordinate, const std::vector> instance_coords) { - /* Add to list if this is a unique mirror*/ + /*check whether the preloaded value exceeds the limit */ size_t limit_x = cbx_unique_module_id_.size(); size_t limit_y = cbx_unique_module_id_[0].size(); - VTR_ASSERT(block_coordinate.x() < limit_x); VTR_ASSERT(block_coordinate.y() < limit_y); add_cb_unique_module(CHANX, block_coordinate); - /* Record the id of unique mirror */ + /* preload the unique block */ set_cb_unique_module_id(CHANX, block_coordinate, get_num_cb_unique_module(CHANX) - 1); - /* Traverse the unique_mirror list and set up its module id */ + /* preload the instances of the unique block. Instance will have the same id + * as the unique block */ for (auto instance_location : instance_coords) { - /* Record the id of unique mirror */ VTR_ASSERT(instance_location.x() < limit_x); VTR_ASSERT(instance_location.y() < limit_y); set_cb_unique_module_id( @@ -607,20 +604,20 @@ void DeviceRRGSB::preload_unique_cbx_module( void DeviceRRGSB::preload_unique_cby_module( const vtr::Point block_coordinate, const std::vector> instance_coords) { - /* Add to list if this is a unique mirror*/ + /*check whether the preloaded value exceeds the limit */ size_t limit_x = cby_unique_module_id_.size(); size_t limit_y = cby_unique_module_id_[0].size(); VTR_ASSERT(block_coordinate.x() < limit_x); VTR_ASSERT(block_coordinate.y() < limit_y); add_cb_unique_module(CHANY, block_coordinate); - /* Record the id of unique mirror */ + /* preload the unique block */ set_cb_unique_module_id(CHANY, block_coordinate, get_num_cb_unique_module(CHANY) - 1); - /* Traverse the unique_mirror list and set up its module id */ + /* preload the instances of the unique block. Instance will have the same id + * as the unique block */ for (auto instance_location : instance_coords) { - /* Record the id of unique mirror */ VTR_ASSERT(instance_location.x() < limit_x); VTR_ASSERT(instance_location.y() < limit_y); set_cb_unique_module_id( @@ -632,7 +629,7 @@ void DeviceRRGSB::preload_unique_cby_module( void DeviceRRGSB::preload_unique_sb_module( const vtr::Point block_coordinate, const std::vector> instance_coords) { - /*input block coordinate should be within gsb coord range*/ + /*check whether the preloaded value exceeds the limit */ VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size()); VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size()); sb_unique_module_.push_back(block_coordinate); @@ -650,6 +647,11 @@ void DeviceRRGSB::preload_unique_sb_module( } } +/*The following four functions will allow us to get +The map between (id,mirror instance coord), (id, unique block coord) +As the unique block and its mirror instances share the same id, we can get the +map between (unique block coord, mirror instance coord) +*/ void DeviceRRGSB::get_id_unique_sb_block_map( std::map>& id_unique_block_map) const { for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 357b70288..2c6f0a8a7 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -494,7 +494,7 @@ int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_name = cmd_context.option_value(cmd, opt_file); std::string file_type = cmd_context.option_value(cmd, opt_type); - /* Write hierarchy to a file */ + /* read unique blocks from a file */ if (file_type == "xml") { return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), @@ -521,7 +521,7 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_name = cmd_context.option_value(cmd, opt_file); std::string file_type = cmd_context.option_value(cmd, opt_type); - /* Write hierarchy to a file */ + /* Write unique blocks to a file */ return write_xml_unique_blocks(openfpga_ctx, file_name.c_str(), file_type.c_str(), cmd_context.option_enable(cmd, opt_verbose)); diff --git a/openfpga/src/fabric/read_write_xml_unique_blocks.h b/openfpga/src/fabric/read_write_xml_unique_blocks.h index e3ab6cb90..36fa75f56 100644 --- a/openfpga/src/fabric/read_write_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_write_xml_unique_blocks.h @@ -2,9 +2,11 @@ #define READ_WRITE_XML_UNIQUE_BLOCKS_H /******************************************************************** - * This file includes the top-level function of this library - * which reads an XML of unique routing blocks to the associated - * data structures device_rr_gsb + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + * -- write device__rr_gsb's info about unique blocks to a xml file *******************************************************************/ #include @@ -32,7 +34,7 @@ /******************************************************************** * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror module of unique module. + * instance is the mirror of unique module. *******************************************************************/ vtr::Point read_xml_unique_instance_info( pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { @@ -157,7 +159,7 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, /* get device_rr_gsb data type and initialize it*/ openfpga::DeviceRRGSB& device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); - /* clear unique modules */ + /* clear unique modules & reserve memory to relavant vectors */ device_rr_gsb.clear_unique_modules(); vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, g_vpr_ctx.device().grid.height() - 1); @@ -179,8 +181,7 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, instance_coords.push_back(instance_coordinate); } } - /* get block coordinate and instance coordinate, try to setup device rr - * gsb */ + /* get block coordinate and instance coordinate, try to setup device_rr_gsb */ if (type == "sb") { device_rr_gsb.preload_unique_sb_module(block_coordinate, instance_coords); @@ -198,6 +199,7 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, return 1; } } + /* As preloading gsb hasn't been developed, we should build gsb using the preloaded cbs and sbs*/ device_rr_gsb.build_gsb_unique_module(); if (verbose_output) { report_unique_module_status_read(openfpga_ctx, true); From 9e283f383d8548d5cc06124ea12a3ec5d8855e12 Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 26 Aug 2024 03:09:19 -0700 Subject: [PATCH 17/50] remove redundant include --- openfpga/src/annotation/device_rr_gsb.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 0537274e5..a9d36de81 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -1,9 +1,6 @@ /************************************************************************ * Member functions for class DeviceRRGSB ***********************************************************************/ - -#include -#include #include "device_rr_gsb.h" #include "rr_gsb_utils.h" #include "vtr_assert.h" From 3c28f84727a7b95bec9776b0a91637675c92413c Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 26 Aug 2024 19:21:26 -0700 Subject: [PATCH 18/50] build bug --- .../src/base/openfpga_build_fabric_template.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 2c6f0a8a7..6898c1de2 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -16,11 +16,11 @@ #include "fabric_key_writer.h" #include "globals.h" #include "openfpga_naming.h" +#include "read_write_xml_unique_blocks.h" #include "read_xml_fabric_key.h" #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" -#include "read_write_xml_unique_blocks.h" #include "rename_modules.h" #include "vtr_log.h" #include "vtr_time.h" @@ -151,7 +151,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } else if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - true == cmd_context.option_enable(cmd, opt_preload)){ + true == cmd_context.option_enable(cmd, opt_preload)) { openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } @@ -500,7 +500,7 @@ int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, file_type.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } else { - VTR_LOG_ERROR("file type %s not supported", file_type); + VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); } } @@ -522,9 +522,13 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write unique blocks to a file */ - return write_xml_unique_blocks(openfpga_ctx, file_name.c_str(), - file_type.c_str(), - cmd_context.option_enable(cmd, opt_verbose)); + if (file_type == "xml") { + return write_xml_unique_blocks(openfpga_ctx, file_name.c_str(), + file_type.c_str(), + cmd_context.option_enable(cmd, opt_verbose)); + } else { + VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); + } } } /* end namespace openfpga */ From 1b0fcaee0fcaadd3550e191885123cd852b4f451 Mon Sep 17 00:00:00 2001 From: Lin Date: Tue, 27 Aug 2024 17:05:13 +0800 Subject: [PATCH 19/50] reformat code --- openfpga/src/annotation/device_rr_gsb.cpp | 3 ++- .../base/openfpga_setup_command_template.h | 5 ++-- .../src/fabric/read_write_xml_unique_blocks.h | 27 +++++++++---------- 3 files changed, 18 insertions(+), 17 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index a9d36de81..33193d000 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -2,6 +2,7 @@ * Member functions for class DeviceRRGSB ***********************************************************************/ #include "device_rr_gsb.h" + #include "rr_gsb_utils.h" #include "vtr_assert.h" #include "vtr_log.h" @@ -647,7 +648,7 @@ void DeviceRRGSB::preload_unique_sb_module( /*The following four functions will allow us to get The map between (id,mirror instance coord), (id, unique block coord) As the unique block and its mirror instances share the same id, we can get the -map between (unique block coord, mirror instance coord) +map between (unique block coord, mirror instance coord) */ void DeviceRRGSB::get_id_unique_sb_block_map( std::map>& id_unique_block_map) const { diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index fe5662000..bfcb88b1e 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -392,8 +392,9 @@ ShellCommandId add_build_fabric_command_template( "identifying the unique GSBs"); /* Add an option '--preload_unique_blocks' */ - shell_cmd.add_option("preload_unique_blocks", false, - "preload unique routing modules from user input xml file"); + shell_cmd.add_option( + "preload_unique_blocks", false, + "preload unique routing modules from user input xml file"); /* Add an option '--duplicate_grid_pin' */ shell_cmd.add_option("duplicate_grid_pin", false, diff --git a/openfpga/src/fabric/read_write_xml_unique_blocks.h b/openfpga/src/fabric/read_write_xml_unique_blocks.h index 36fa75f56..e50e0b243 100644 --- a/openfpga/src/fabric/read_write_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_write_xml_unique_blocks.h @@ -47,10 +47,8 @@ vtr::Point read_xml_unique_instance_info( template void report_unique_module_status_read(T& openfpga_ctx, bool verbose_output) { /* Report the stats */ - VTR_LOGV( - verbose_output, - "Read %lu unique X-direction connection blocks ", - openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX)); + VTR_LOGV(verbose_output, "Read %lu unique X-direction connection blocks ", + openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX)); VTR_LOGV( verbose_output, @@ -89,7 +87,6 @@ void report_unique_module_status_read(T& openfpga_ctx, bool verbose_output) { 1.)); } - template void report_unique_module_status_write(T& openfpga_ctx, bool verbose_output) { /* Report the stats */ @@ -161,8 +158,8 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, openfpga::DeviceRRGSB& device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); /* clear unique modules & reserve memory to relavant vectors */ device_rr_gsb.clear_unique_modules(); - vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, - g_vpr_ctx.device().grid.height() - 1); + vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, + g_vpr_ctx.device().grid.height() - 1); device_rr_gsb.reserve_unique_modules(grid_coord); /* load unique blocks xml file and set up device_rr_gdb */ for (pugi::xml_node xml_block_info : xml_root.children()) { @@ -181,16 +178,17 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, instance_coords.push_back(instance_coordinate); } } - /* get block coordinate and instance coordinate, try to setup device_rr_gsb */ + /* get block coordinate and instance coordinate, try to setup + * device_rr_gsb */ if (type == "sb") { device_rr_gsb.preload_unique_sb_module(block_coordinate, instance_coords); } else if (type == "cby") { device_rr_gsb.preload_unique_cby_module(block_coordinate, - instance_coords); + instance_coords); } else if (type == "cbx") { device_rr_gsb.preload_unique_cbx_module(block_coordinate, - instance_coords); + instance_coords); } else { VTR_LOG_ERROR("Unexpected type!"); } @@ -199,7 +197,8 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, return 1; } } - /* As preloading gsb hasn't been developed, we should build gsb using the preloaded cbs and sbs*/ + /* As preloading gsb hasn't been developed, we should build gsb using the + * preloaded cbs and sbs*/ device_rr_gsb.build_gsb_unique_module(); if (verbose_output) { report_unique_module_status_read(openfpga_ctx, true); @@ -207,7 +206,7 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); } - + return 0; } @@ -232,8 +231,8 @@ int write_xml_block( for (const auto& instance_info : id_instance_map[pair.first]) { if (instance_info.x() == pair.second.x() && instance_info.y() == pair.second.y()) { - ; - }else{ + ; + } else { openfpga::write_tab_to_file(fp, 2); fp << " Date: Wed, 28 Aug 2024 15:45:19 +0800 Subject: [PATCH 20/50] mod according to code review --- .../src/base/openfpga_build_fabric_template.h | 2 ++ .../base/openfpga_setup_command_template.h | 21 ++++++++++++------- .../src/fabric/read_write_xml_unique_blocks.h | 10 ++++++++- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 6898c1de2..6795af4e8 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -501,6 +501,7 @@ int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, cmd_context.option_enable(cmd, opt_verbose)); } else { VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); + return CMD_EXEC_FATAL_ERROR; } } @@ -528,6 +529,7 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, cmd_context.option_enable(cmd, opt_verbose)); } else { VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); + return CMD_EXEC_FATAL_ERROR; } } } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index bfcb88b1e..f73e3e01d 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -947,13 +947,15 @@ ShellCommandId add_read_unique_blocks_command_template( Command shell_cmd("read_unique_blocks"); /* Add an option '--file' */ - CommandOptionId opt_file = - shell_cmd.add_option("file", true, "specify the unique blocks xml file"); + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, "specify the file which contains unique block information"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); /* Add an option '--type' */ - CommandOptionId opt_type = shell_cmd.add_option( - "type", true, "specify the type of the unique blocks xml file"); + CommandOptionId opt_type = + shell_cmd.add_option("type", true, + "Specify the type of the unique blocks file " + "[xml|bin]. If not specified, by default it is XML."); shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING); /* Add an option '--verbose' */ @@ -984,13 +986,16 @@ ShellCommandId add_write_unique_blocks_command_template( Command shell_cmd("write_unique_blocks"); /* Add an option '--file' */ - CommandOptionId opt_file = - shell_cmd.add_option("file", true, "specify the unique blocks xml file"); + CommandOptionId opt_file = shell_cmd.add_option( + "file", true, + "specify the file which we will write unique block information to"); shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING); /* Add an option '--type' */ - CommandOptionId opt_type = shell_cmd.add_option( - "type", true, "specify the type of the unique blocks xml file"); + CommandOptionId opt_type = + shell_cmd.add_option("type", true, + "Specify the type of the unique blocks file " + "[xml|bin]. If not specified, by default it is XML."); shell_cmd.set_option_require_value(opt_type, openfpga::OPT_STRING); /* Add an option '--verbose' */ diff --git a/openfpga/src/fabric/read_write_xml_unique_blocks.h b/openfpga/src/fabric/read_write_xml_unique_blocks.h index e50e0b243..f7c3091ef 100644 --- a/openfpga/src/fabric/read_write_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_write_xml_unique_blocks.h @@ -36,6 +36,9 @@ * Parse XML codes of a to an object of device_rr_gsb * instance is the mirror of unique module. *******************************************************************/ +namespace openfpga { +vtr::Point read_xml_unique_instance_info; +int write_xml_block; vtr::Point read_xml_unique_instance_info( pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); @@ -190,7 +193,9 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, device_rr_gsb.preload_unique_cbx_module(block_coordinate, instance_coords); } else { - VTR_LOG_ERROR("Unexpected type!"); + archfpga_throw(loc_data.filename_c_str(), + loc_data.line(xml_block_info), + "Invalid block type '%s'\n", type); } } else { bad_tag(xml_block_info, loc_data, xml_root, {"block"}); @@ -202,6 +207,7 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, device_rr_gsb.build_gsb_unique_module(); if (verbose_output) { report_unique_module_status_read(openfpga_ctx, true); + return 0; } } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); @@ -294,8 +300,10 @@ int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, fp.close(); if (verbose_output) { report_unique_module_status_write(openfpga_ctx, true); + return err_code; } return err_code; } +} // namespace openfpga #endif From d4028b4e6f09dbe61a49469297a6815b62fc55da Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 28 Aug 2024 16:31:16 +0800 Subject: [PATCH 21/50] modification no build warning now --- .../src/io/io_xml_unique_blocks.cpp | 61 +++++++++++++++++ .../src/io/io_xml_unique_blocks.h | 25 +++++++ .../src/fabric/read_write_xml_unique_blocks.h | 66 +++---------------- 3 files changed, 94 insertions(+), 58 deletions(-) create mode 100644 libs/libfabrickey/src/io/io_xml_unique_blocks.cpp create mode 100644 libs/libfabrickey/src/io/io_xml_unique_blocks.h diff --git a/libs/libfabrickey/src/io/io_xml_unique_blocks.cpp b/libs/libfabrickey/src/io/io_xml_unique_blocks.cpp new file mode 100644 index 000000000..2cfab2000 --- /dev/null +++ b/libs/libfabrickey/src/io/io_xml_unique_blocks.cpp @@ -0,0 +1,61 @@ +#include +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "io_xml_unique_blocks.h" +#include "openfpga_digest.h" +#include "read_xml_util.h" +#include "write_xml_utils.h" + +namespace openfpga { +vtr::Point read_xml_unique_instance_info( + pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { + int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); + int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); + vtr::Point instance_coordinate(instance_x, instance_y); + return instance_coordinate; +} + +int write_xml_block( + std::map>& id_unique_block_map, + std::map>>& id_instance_map, + std::fstream& fp, std::string type) { + /* Validate the file stream */ + if (false == openfpga::valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + for (const auto& pair : id_unique_block_map) { + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + + for (const auto& instance_info : id_instance_map[pair.first]) { + if (instance_info.x() == pair.second.x() && + instance_info.y() == pair.second.y()) { + ; + } else { + openfpga::write_tab_to_file(fp, 2); + fp << "" + << "\n"; + } + } + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + } + + return CMD_EXEC_SUCCESS; +} +} // namespace openfpga diff --git a/libs/libfabrickey/src/io/io_xml_unique_blocks.h b/libs/libfabrickey/src/io/io_xml_unique_blocks.h new file mode 100644 index 000000000..25a7f812e --- /dev/null +++ b/libs/libfabrickey/src/io/io_xml_unique_blocks.h @@ -0,0 +1,25 @@ +#ifndef IO_XML_UNIQUE_BLOCKS_H +#define IO_XML_UNIQUE_BLOCKS_H + +#include + +#include "pugixml.hpp" +#include "pugixml_util.hpp" +#include "vtr_geometry.h" +/******************************************************************** + * Function declaration + *******************************************************************/ + +namespace openfpga { // Begin namespace openfpga + +vtr::Point read_xml_unique_instance_info( + pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data); + +int write_xml_block( + std::map>& id_unique_block_map, + std::map>>& id_instance_map, + std::fstream& fp, std::string type); + +} // End of namespace openfpga + +#endif diff --git a/openfpga/src/fabric/read_write_xml_unique_blocks.h b/openfpga/src/fabric/read_write_xml_unique_blocks.h index f7c3091ef..56ad3dcaa 100644 --- a/openfpga/src/fabric/read_write_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_write_xml_unique_blocks.h @@ -26,8 +26,8 @@ /* Headers from libarchfpga */ #include "arch_error.h" #include "device_rr_gsb_utils.h" +#include "io_xml_unique_blocks.h" #include "openfpga_digest.h" -#include "read_write_xml_unique_blocks.h" #include "read_xml_util.h" #include "rr_gsb.h" #include "write_xml_utils.h" @@ -37,16 +37,6 @@ * instance is the mirror of unique module. *******************************************************************/ namespace openfpga { -vtr::Point read_xml_unique_instance_info; -int write_xml_block; -vtr::Point read_xml_unique_instance_info( - pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { - int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); - int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); - vtr::Point instance_coordinate(instance_x, instance_y); - return instance_coordinate; -} - template void report_unique_module_status_read(T& openfpga_ctx, bool verbose_output) { /* Report the stats */ @@ -199,7 +189,6 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, } } else { bad_tag(xml_block_info, loc_data, xml_root, {"block"}); - return 1; } } /* As preloading gsb hasn't been developed, we should build gsb using the @@ -207,53 +196,11 @@ int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, device_rr_gsb.build_gsb_unique_module(); if (verbose_output) { report_unique_module_status_read(openfpga_ctx, true); - return 0; } + return CMD_EXEC_SUCCESS; } catch (pugiutil::XmlError& e) { archfpga_throw(file_name, e.line(), "%s", e.what()); } - - return 0; -} - -int write_xml_block( - std::map>& id_unique_block_map, - std::map>>& id_instance_map, - std::fstream& fp, std::string type) { - /* Validate the file stream */ - if (false == openfpga::valid_file_stream(fp)) { - return 2; - } - for (const auto& pair : id_unique_block_map) { - openfpga::write_tab_to_file(fp, 1); - fp << "" - << "\n"; - - for (const auto& instance_info : id_instance_map[pair.first]) { - if (instance_info.x() == pair.second.x() && - instance_info.y() == pair.second.y()) { - ; - } else { - openfpga::write_tab_to_file(fp, 2); - fp << "" - << "\n"; - } - } - openfpga::write_tab_to_file(fp, 1); - fp << "" - << "\n"; - } - - return 0; } template @@ -300,10 +247,13 @@ int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, fp.close(); if (verbose_output) { report_unique_module_status_write(openfpga_ctx, true); - return err_code; } - return err_code; -} + + if (err_code >= 1) { + return CMD_EXEC_FATAL_ERROR; + } else { + return CMD_EXEC_SUCCESS; + } } // namespace openfpga #endif From 0a14b2fa652ff4d3c7afd9f8fd1521d520252179 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 28 Aug 2024 17:26:50 +0800 Subject: [PATCH 22/50] pass device_rr_gsb instead of openfpga_ctx --- .../src/io/io_xml_unique_blocks.cpp | 61 ----- .../src/io/io_xml_unique_blocks.h | 25 -- .../src/base/openfpga_build_fabric_template.h | 11 +- .../src/fabric/read_write_xml_unique_blocks.h | 259 ------------------ .../src/fabric/read_xml_unique_blocks.cpp | 158 +++++++++++ openfpga/src/fabric/read_xml_unique_blocks.h | 40 +++ .../src/fabric/write_xml_unique_blocks.cpp | 173 ++++++++++++ openfpga/src/fabric/write_xml_unique_blocks.h | 42 +++ 8 files changed, 419 insertions(+), 350 deletions(-) delete mode 100644 libs/libfabrickey/src/io/io_xml_unique_blocks.cpp delete mode 100644 libs/libfabrickey/src/io/io_xml_unique_blocks.h delete mode 100644 openfpga/src/fabric/read_write_xml_unique_blocks.h create mode 100644 openfpga/src/fabric/read_xml_unique_blocks.cpp create mode 100644 openfpga/src/fabric/read_xml_unique_blocks.h create mode 100644 openfpga/src/fabric/write_xml_unique_blocks.cpp create mode 100644 openfpga/src/fabric/write_xml_unique_blocks.h diff --git a/libs/libfabrickey/src/io/io_xml_unique_blocks.cpp b/libs/libfabrickey/src/io/io_xml_unique_blocks.cpp deleted file mode 100644 index 2cfab2000..000000000 --- a/libs/libfabrickey/src/io/io_xml_unique_blocks.cpp +++ /dev/null @@ -1,61 +0,0 @@ -#include -/* Headers from vtr util library */ -#include "vtr_assert.h" -#include "vtr_time.h" - -/* Headers from libarchfpga */ -#include "arch_error.h" -#include "io_xml_unique_blocks.h" -#include "openfpga_digest.h" -#include "read_xml_util.h" -#include "write_xml_utils.h" - -namespace openfpga { -vtr::Point read_xml_unique_instance_info( - pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { - int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); - int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); - vtr::Point instance_coordinate(instance_x, instance_y); - return instance_coordinate; -} - -int write_xml_block( - std::map>& id_unique_block_map, - std::map>>& id_instance_map, - std::fstream& fp, std::string type) { - /* Validate the file stream */ - if (false == openfpga::valid_file_stream(fp)) { - return CMD_EXEC_FATAL_ERROR; - } - for (const auto& pair : id_unique_block_map) { - openfpga::write_tab_to_file(fp, 1); - fp << "" - << "\n"; - - for (const auto& instance_info : id_instance_map[pair.first]) { - if (instance_info.x() == pair.second.x() && - instance_info.y() == pair.second.y()) { - ; - } else { - openfpga::write_tab_to_file(fp, 2); - fp << "" - << "\n"; - } - } - openfpga::write_tab_to_file(fp, 1); - fp << "" - << "\n"; - } - - return CMD_EXEC_SUCCESS; -} -} // namespace openfpga diff --git a/libs/libfabrickey/src/io/io_xml_unique_blocks.h b/libs/libfabrickey/src/io/io_xml_unique_blocks.h deleted file mode 100644 index 25a7f812e..000000000 --- a/libs/libfabrickey/src/io/io_xml_unique_blocks.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef IO_XML_UNIQUE_BLOCKS_H -#define IO_XML_UNIQUE_BLOCKS_H - -#include - -#include "pugixml.hpp" -#include "pugixml_util.hpp" -#include "vtr_geometry.h" -/******************************************************************** - * Function declaration - *******************************************************************/ - -namespace openfpga { // Begin namespace openfpga - -vtr::Point read_xml_unique_instance_info( - pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data); - -int write_xml_block( - std::map>& id_unique_block_map, - std::map>>& id_instance_map, - std::fstream& fp, std::string type); - -} // End of namespace openfpga - -#endif diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 6795af4e8..466702530 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -16,16 +16,17 @@ #include "fabric_key_writer.h" #include "globals.h" #include "openfpga_naming.h" -#include "read_write_xml_unique_blocks.h" #include "read_xml_fabric_key.h" #include "read_xml_io_name_map.h" #include "read_xml_module_name_map.h" #include "read_xml_tile_config.h" +#include "read_xml_unique_blocks.h" #include "rename_modules.h" #include "vtr_log.h" #include "vtr_time.h" #include "write_xml_fabric_pin_physical_location.h" #include "write_xml_module_name_map.h" +#include "write_xml_unique_blocks.h" /* begin namespace openfpga */ namespace openfpga { @@ -496,8 +497,8 @@ int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_type = cmd_context.option_value(cmd, opt_type); /* read unique blocks from a file */ if (file_type == "xml") { - return read_xml_unique_blocks(openfpga_ctx, file_name.c_str(), - file_type.c_str(), + return read_xml_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } else { VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); @@ -524,8 +525,8 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, /* Write unique blocks to a file */ if (file_type == "xml") { - return write_xml_unique_blocks(openfpga_ctx, file_name.c_str(), - file_type.c_str(), + return write_xml_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + file_name.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } else { VTR_LOG_ERROR("file type %s not supported", file_type.c_str()); diff --git a/openfpga/src/fabric/read_write_xml_unique_blocks.h b/openfpga/src/fabric/read_write_xml_unique_blocks.h deleted file mode 100644 index 56ad3dcaa..000000000 --- a/openfpga/src/fabric/read_write_xml_unique_blocks.h +++ /dev/null @@ -1,259 +0,0 @@ -#ifndef READ_WRITE_XML_UNIQUE_BLOCKS_H -#define READ_WRITE_XML_UNIQUE_BLOCKS_H - -/******************************************************************** - * This file includes the top-level functions of this library - * which includes: - * -- reads an XML file of unique blocks to the associated - * data structures: device_rr_gsb - * -- write device__rr_gsb's info about unique blocks to a xml file - *******************************************************************/ - -#include - -/* Headers from pugi XML library */ -#include "pugixml.hpp" -#include "pugixml_util.hpp" - -/* Headers from vtr util library */ -#include "vtr_assert.h" -#include "vtr_log.h" -#include "vtr_time.h" - -/* Headers from libopenfpga util library */ -#include "openfpga_port_parser.h" - -/* Headers from libarchfpga */ -#include "arch_error.h" -#include "device_rr_gsb_utils.h" -#include "io_xml_unique_blocks.h" -#include "openfpga_digest.h" -#include "read_xml_util.h" -#include "rr_gsb.h" -#include "write_xml_utils.h" - -/******************************************************************** - * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror of unique module. - *******************************************************************/ -namespace openfpga { -template -void report_unique_module_status_read(T& openfpga_ctx, bool verbose_output) { - /* Report the stats */ - VTR_LOGV(verbose_output, "Read %lu unique X-direction connection blocks ", - openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX)); - - VTR_LOGV( - verbose_output, - "Read %lu unique Y-direction connection blocks from a total of %d " - "(compression rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY), - find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY), - 100. * - ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), - CHANY) / - (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - - 1.)); - - VTR_LOGV( - verbose_output, - "Read %lu unique switch blocks from a total of %d (compression " - "rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(), - find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(), - g_vpr_ctx.device().rr_graph), - 100. * ((float)find_device_rr_gsb_num_sb_modules( - openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / - (float)openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - - 1.)); - - VTR_LOG( - "Read %lu unique general switch blocks from a total of %d " - "(compression " - "rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(), - find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb(), - g_vpr_ctx.device().rr_graph), - 100. * ((float)find_device_rr_gsb_num_gsb_modules( - openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / - (float)openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - - 1.)); -} - -template -void report_unique_module_status_write(T& openfpga_ctx, bool verbose_output) { - /* Report the stats */ - VTR_LOGV( - verbose_output, - "Write %lu unique X-direction connection blocks from a total of %d " - "(compression rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX), - find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANX), - 100. * - ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), - CHANX) / - (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANX) - - 1.)); - - VTR_LOGV( - verbose_output, - "Write %lu unique Y-direction connection blocks from a total of %d " - "(compression rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY), - find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), CHANY), - 100. * - ((float)find_device_rr_gsb_num_cb_modules(openfpga_ctx.device_rr_gsb(), - CHANY) / - (float)openfpga_ctx.device_rr_gsb().get_num_cb_unique_module(CHANY) - - 1.)); - - VTR_LOGV( - verbose_output, - "Write %lu unique switch blocks from a total of %d (compression " - "rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_sb_unique_module(), - find_device_rr_gsb_num_sb_modules(openfpga_ctx.device_rr_gsb(), - g_vpr_ctx.device().rr_graph), - 100. * ((float)find_device_rr_gsb_num_sb_modules( - openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / - (float)openfpga_ctx.device_rr_gsb().get_num_sb_unique_module() - - 1.)); - - VTR_LOG( - "Write %lu unique general switch blocks from a total of %d " - "(compression " - "rate=%.2f%)\n", - openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module(), - find_device_rr_gsb_num_gsb_modules(openfpga_ctx.device_rr_gsb(), - g_vpr_ctx.device().rr_graph), - 100. * ((float)find_device_rr_gsb_num_gsb_modules( - openfpga_ctx.device_rr_gsb(), g_vpr_ctx.device().rr_graph) / - (float)openfpga_ctx.device_rr_gsb().get_num_gsb_unique_module() - - 1.)); -} -/******************************************************************** - * Parse XML codes about to an object of device_rr_gsb - *******************************************************************/ -template -int read_xml_unique_blocks(T& openfpga_ctx, const char* file_name, - const char* file_type, bool verbose_output) { - vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); - /* Parse the file */ - pugi::xml_document doc; - pugiutil::loc_data loc_data; - VTR_ASSERT(strcmp(file_type, "xml") == 0); - try { - loc_data = pugiutil::load_xml(doc, file_name); - - pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); - - /* get device_rr_gsb data type and initialize it*/ - openfpga::DeviceRRGSB& device_rr_gsb = openfpga_ctx.mutable_device_rr_gsb(); - /* clear unique modules & reserve memory to relavant vectors */ - device_rr_gsb.clear_unique_modules(); - vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, - g_vpr_ctx.device().grid.height() - 1); - device_rr_gsb.reserve_unique_modules(grid_coord); - /* load unique blocks xml file and set up device_rr_gdb */ - for (pugi::xml_node xml_block_info : xml_root.children()) { - /* Error out if the XML child has an invalid name! */ - if (xml_block_info.name() == std::string("block")) { - std::string type = - get_attribute(xml_block_info, "type", loc_data).as_string(); - int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); - int block_y = get_attribute(xml_block_info, "y", loc_data).as_int(); - vtr::Point block_coordinate(block_x, block_y); - std::vector> instance_coords; - for (pugi::xml_node xml_instance_info : xml_block_info.children()) { - if (xml_instance_info.name() == std::string("instance")) { - auto instance_coordinate = - read_xml_unique_instance_info(xml_instance_info, loc_data); - instance_coords.push_back(instance_coordinate); - } - } - /* get block coordinate and instance coordinate, try to setup - * device_rr_gsb */ - if (type == "sb") { - device_rr_gsb.preload_unique_sb_module(block_coordinate, - instance_coords); - } else if (type == "cby") { - device_rr_gsb.preload_unique_cby_module(block_coordinate, - instance_coords); - } else if (type == "cbx") { - device_rr_gsb.preload_unique_cbx_module(block_coordinate, - instance_coords); - } else { - archfpga_throw(loc_data.filename_c_str(), - loc_data.line(xml_block_info), - "Invalid block type '%s'\n", type); - } - } else { - bad_tag(xml_block_info, loc_data, xml_root, {"block"}); - } - } - /* As preloading gsb hasn't been developed, we should build gsb using the - * preloaded cbs and sbs*/ - device_rr_gsb.build_gsb_unique_module(); - if (verbose_output) { - report_unique_module_status_read(openfpga_ctx, true); - } - return CMD_EXEC_SUCCESS; - } catch (pugiutil::XmlError& e) { - archfpga_throw(file_name, e.line(), "%s", e.what()); - } -} - -template -int write_xml_unique_blocks(const T& openfpga_ctx, const char* fname, - const char* file_type, bool verbose_output) { - vtr::ScopedStartFinishTimer timer("Write unique blocks..."); - VTR_ASSERT(strcmp(file_type, "xml") == 0); - /* Create a file handler */ - std::fstream fp; - /* Open the file stream */ - fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); - - /* Validate the file stream */ - openfpga::check_file_stream(fname, fp); - - /* Write the root node */ - fp << "" - << "\n"; - - int err_code = 0; - std::map> id_unique_block_map; - std::map>> id_instance_map; - openfpga_ctx.device_rr_gsb().get_id_unique_sb_block_map(id_unique_block_map); - openfpga_ctx.device_rr_gsb().get_id_sb_instance_map(id_instance_map); - err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "sb"); - - id_unique_block_map.clear(); - id_instance_map.clear(); - openfpga_ctx.device_rr_gsb().get_id_unique_cbx_block_map(id_unique_block_map); - openfpga_ctx.device_rr_gsb().get_id_cbx_instance_map(id_instance_map); - err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cbx"); - - id_unique_block_map.clear(); - id_instance_map.clear(); - openfpga_ctx.device_rr_gsb().get_id_unique_cby_block_map(id_unique_block_map); - openfpga_ctx.device_rr_gsb().get_id_cby_instance_map(id_instance_map); - err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cby"); - - /* Finish writing the root node */ - fp << "" - << "\n"; - - /* Close the file stream */ - fp.close(); - if (verbose_output) { - report_unique_module_status_write(openfpga_ctx, true); - } - - if (err_code >= 1) { - return CMD_EXEC_FATAL_ERROR; - } else { - return CMD_EXEC_SUCCESS; - } -} // namespace openfpga - -#endif diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp new file mode 100644 index 000000000..e754aef40 --- /dev/null +++ b/openfpga/src/fabric/read_xml_unique_blocks.cpp @@ -0,0 +1,158 @@ + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + * -- write device__rr_gsb's info about unique blocks to a xml file + *******************************************************************/ + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "openfpga_digest.h" +#include "read_xml_unique_blocks.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "write_xml_utils.h" + +/******************************************************************** + * Parse XML codes of a to an object of device_rr_gsb + * instance is the mirror of unique module. + *******************************************************************/ +namespace openfpga { + +vtr::Point read_xml_unique_instance_info( + pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { + int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); + int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); + vtr::Point instance_coordinate(instance_x, instance_y); + return instance_coordinate; +} + +void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, + bool verbose_output) { + /* Report the stats */ + VTR_LOGV( + verbose_output, + "Read %lu unique X-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANX), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANX) - + 1.)); + VTR_LOGV( + verbose_output, + "Read %lu unique Y-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANY), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANY) - + 1.)); + + VTR_LOGV(verbose_output, + "Read %lu unique switch blocks from a total of %d (compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_sb_unique_module(), + find_device_rr_gsb_num_sb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_sb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_sb_unique_module() - + 1.)); + + VTR_LOG( + "Read %lu unique general switch blocks from a total of %d " + "(compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_gsb_unique_module(), + find_device_rr_gsb_num_gsb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_gsb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_gsb_unique_module() - + 1.)); +} + +/******************************************************************** + * Parse XML codes about to an object of device_rr_gsb + *******************************************************************/ +int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output) { + vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); + /* Parse the file */ + pugi::xml_document doc; + pugiutil::loc_data loc_data; + try { + loc_data = pugiutil::load_xml(doc, file_name); + + pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); + /* clear unique modules & reserve memory to relavant vectors */ + device_rr_gsb.clear_unique_modules(); + vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, + g_vpr_ctx.device().grid.height() - 1); + device_rr_gsb.reserve_unique_modules(grid_coord); + + /* load unique blocks xml file and set up device_rr_gdb */ + for (pugi::xml_node xml_block_info : xml_root.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_block_info.name() == std::string("block")) { + std::string type = + get_attribute(xml_block_info, "type", loc_data).as_string(); + int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); + int block_y = get_attribute(xml_block_info, "y", loc_data).as_int(); + vtr::Point block_coordinate(block_x, block_y); + std::vector> instance_coords; + for (pugi::xml_node xml_instance_info : xml_block_info.children()) { + if (xml_instance_info.name() == std::string("instance")) { + auto instance_coordinate = + read_xml_unique_instance_info(xml_instance_info, loc_data); + instance_coords.push_back(instance_coordinate); + } + } + /* get block coordinate and instance coordinate, try to setup + * device_rr_gsb */ + if (type == "sb") { + device_rr_gsb.preload_unique_sb_module(block_coordinate, + instance_coords); + } else if (type == "cby") { + device_rr_gsb.preload_unique_cby_module(block_coordinate, + instance_coords); + } else if (type == "cbx") { + device_rr_gsb.preload_unique_cbx_module(block_coordinate, + instance_coords); + } else { + archfpga_throw(loc_data.filename_c_str(), + loc_data.line(xml_block_info), + "Invalid block type '%s'\n", type); + } + } else { + bad_tag(xml_block_info, loc_data, xml_root, {"block"}); + } + } + /* As preloading gsb hasn't been developed, we should build gsb using the + * preloaded cbs and sbs*/ + device_rr_gsb.build_gsb_unique_module(); + if (verbose_output) { + report_unique_module_status_read(device_rr_gsb, true); + } + return CMD_EXEC_SUCCESS; + } catch (pugiutil::XmlError& e) { + archfpga_throw(file_name, e.line(), "%s", e.what()); + } +} +} // namespace openfpga diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h new file mode 100644 index 000000000..c2e3a06cd --- /dev/null +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -0,0 +1,40 @@ +#ifndef READ_XML_UNIQUE_BLOCKS_H +#define READ_XML_UNIQUE_BLOCKS_H + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + * -- write device__rr_gsb's info about unique blocks to a xml file + *******************************************************************/ + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" + +/******************************************************************** + * Parse XML codes of a to an object of device_rr_gsb + * instance is the mirror of unique module. + *******************************************************************/ +namespace openfpga { + +vtr::Point read_xml_unique_instance_info( + pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data); +void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, + bool verbose_output); +int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, + bool verbose_output); +} // namespace openfpga +#endif diff --git a/openfpga/src/fabric/write_xml_unique_blocks.cpp b/openfpga/src/fabric/write_xml_unique_blocks.cpp new file mode 100644 index 000000000..563755526 --- /dev/null +++ b/openfpga/src/fabric/write_xml_unique_blocks.cpp @@ -0,0 +1,173 @@ + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + * -- write device__rr_gsb's info about unique blocks to a xml file + *******************************************************************/ + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "command_exit_codes.h" +#include "device_rr_gsb_utils.h" +#include "openfpga_digest.h" +#include "read_xml_util.h" +#include "rr_gsb.h" +#include "write_xml_unique_blocks.h" +#include "write_xml_utils.h" +/******************************************************************** + * Parse XML codes of a to an object of device_rr_gsb + * instance is the mirror of unique module. + *******************************************************************/ +namespace openfpga { + +int write_xml_block( + std::map>& id_unique_block_map, + std::map>>& id_instance_map, + std::fstream& fp, std::string type) { + /* Validate the file stream */ + if (false == openfpga::valid_file_stream(fp)) { + return CMD_EXEC_FATAL_ERROR; + } + for (const auto& pair : id_unique_block_map) { + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + + for (const auto& instance_info : id_instance_map[pair.first]) { + if (instance_info.x() == pair.second.x() && + instance_info.y() == pair.second.y()) { + ; + } else { + openfpga::write_tab_to_file(fp, 2); + fp << "" + << "\n"; + } + } + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + } + + return CMD_EXEC_SUCCESS; +} + +void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, + bool verbose_output) { + /* Report the stats */ + VTR_LOGV( + verbose_output, + "Write %lu unique X-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANX), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANX) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANX) - + 1.)); + + VTR_LOGV( + verbose_output, + "Write %lu unique Y-direction connection blocks from a total of %d " + "(compression rate=%.2f%)\n", + device_rr_gsb.get_num_cb_unique_module(CHANY), + find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY), + 100. * ((float)find_device_rr_gsb_num_cb_modules(device_rr_gsb, CHANY) / + (float)device_rr_gsb.get_num_cb_unique_module(CHANY) - + 1.)); + + VTR_LOGV(verbose_output, + "Write %lu unique switch blocks from a total of %d (compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_sb_unique_module(), + find_device_rr_gsb_num_sb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_sb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_sb_unique_module() - + 1.)); + + VTR_LOG( + "Write %lu unique general switch blocks from a total of %d " + "(compression " + "rate=%.2f%)\n", + device_rr_gsb.get_num_gsb_unique_module(), + find_device_rr_gsb_num_gsb_modules(device_rr_gsb, + g_vpr_ctx.device().rr_graph), + 100. * ((float)find_device_rr_gsb_num_gsb_modules( + device_rr_gsb, g_vpr_ctx.device().rr_graph) / + (float)device_rr_gsb.get_num_gsb_unique_module() - + 1.)); +} + +int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output) { + vtr::ScopedStartFinishTimer timer("Write unique blocks..."); + /* Create a file handler */ + std::fstream fp; + /* Open the file stream */ + fp.open(std::string(fname), std::fstream::out | std::fstream::trunc); + + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + /* Write the root node */ + fp << "" + << "\n"; + + int err_code = 0; + std::map> id_unique_block_map; + std::map>> id_instance_map; + device_rr_gsb.get_id_unique_sb_block_map(id_unique_block_map); + device_rr_gsb.get_id_sb_instance_map(id_instance_map); + err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "sb"); + + id_unique_block_map.clear(); + id_instance_map.clear(); + device_rr_gsb.get_id_unique_cbx_block_map(id_unique_block_map); + device_rr_gsb.get_id_cbx_instance_map(id_instance_map); + err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cbx"); + + id_unique_block_map.clear(); + id_instance_map.clear(); + device_rr_gsb.get_id_unique_cby_block_map(id_unique_block_map); + device_rr_gsb.get_id_cby_instance_map(id_instance_map); + err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cby"); + + /* Finish writing the root node */ + fp << "" + << "\n"; + + /* Close the file stream */ + fp.close(); + if (verbose_output) { + report_unique_module_status_write(device_rr_gsb, true); + } + + if (err_code >= 1) { + return CMD_EXEC_FATAL_ERROR; + } else { + return CMD_EXEC_SUCCESS; + } +} +} // namespace openfpga diff --git a/openfpga/src/fabric/write_xml_unique_blocks.h b/openfpga/src/fabric/write_xml_unique_blocks.h new file mode 100644 index 000000000..f8aa5959d --- /dev/null +++ b/openfpga/src/fabric/write_xml_unique_blocks.h @@ -0,0 +1,42 @@ +#ifndef WRITE_XML_UNIQUE_BLOCKS_H +#define WRITE_XML_UNIQUE_BLOCKS_H + +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb + * -- write device__rr_gsb's info about unique blocks to a xml file + *******************************************************************/ + +#include + +/* Headers from pugi XML library */ +#include "pugixml.hpp" +#include "pugixml_util.hpp" + +/* Headers from vtr util library */ +#include "vtr_assert.h" +#include "vtr_log.h" +#include "vtr_time.h" + +/* Headers from libarchfpga */ +#include "arch_error.h" +#include "device_rr_gsb_utils.h" + +/******************************************************************** + * Parse XML codes of a to an object of device_rr_gsb + * instance is the mirror of unique module. + *******************************************************************/ +namespace openfpga { + +int write_xml_block( + std::map>& id_unique_block_map, + std::map>>& id_instance_map, + std::fstream& fp, std::string type); +void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, + bool verbose_output); +int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, + bool verbose_output); +} // namespace openfpga +#endif From df05c904dbf8a662c6a524c9466487301a72e6bd Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 28 Aug 2024 17:41:41 +0800 Subject: [PATCH 23/50] make the read block coord and read instance coords clearer --- .../src/base/openfpga_build_fabric_template.h | 2 +- .../src/fabric/read_xml_unique_blocks.cpp | 42 +++++++++++-------- openfpga/src/fabric/read_xml_unique_blocks.h | 9 +++- 3 files changed, 33 insertions(+), 20 deletions(-) diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 466702530..18825759e 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -525,7 +525,7 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, /* Write unique blocks to a file */ if (file_type == "xml") { - return write_xml_unique_blocks(openfpga_ctx.mutable_device_rr_gsb(), + return write_xml_unique_blocks(openfpga_ctx.device_rr_gsb(), file_name.c_str(), cmd_context.option_enable(cmd, opt_verbose)); } else { diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp index e754aef40..0888e390c 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.cpp +++ b/openfpga/src/fabric/read_xml_unique_blocks.cpp @@ -34,12 +34,26 @@ *******************************************************************/ namespace openfpga { -vtr::Point read_xml_unique_instance_info( - pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data) { - int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); - int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); - vtr::Point instance_coordinate(instance_x, instance_y); - return instance_coordinate; +std::vector> read_xml_unique_instance_coords( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) { + std::vector> instance_coords; + for (pugi::xml_node xml_instance_info : xml_block_info.children()) { + if (xml_instance_info.name() == std::string("instance")) { + int instance_x = get_attribute(xml_instance_info, "x", loc_data).as_int(); + int instance_y = get_attribute(xml_instance_info, "y", loc_data).as_int(); + vtr::Point instance_coordinate(instance_x, instance_y); + instance_coords.push_back(instance_coordinate); + } + } + return instance_coords; +} + +vtr::Point read_xml_unique_block_coord( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) { + int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); + int block_y = get_attribute(xml_block_info, "y", loc_data).as_int(); + vtr::Point block_coordinate(block_x, block_y); + return block_coordinate; } void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, @@ -113,17 +127,11 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, if (xml_block_info.name() == std::string("block")) { std::string type = get_attribute(xml_block_info, "type", loc_data).as_string(); - int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); - int block_y = get_attribute(xml_block_info, "y", loc_data).as_int(); - vtr::Point block_coordinate(block_x, block_y); - std::vector> instance_coords; - for (pugi::xml_node xml_instance_info : xml_block_info.children()) { - if (xml_instance_info.name() == std::string("instance")) { - auto instance_coordinate = - read_xml_unique_instance_info(xml_instance_info, loc_data); - instance_coords.push_back(instance_coordinate); - } - } + vtr::Point block_coordinate = + read_xml_unique_block_coord(xml_block_info, loc_data); + std::vector> instance_coords = + read_xml_unique_instance_coords(xml_block_info, loc_data); + /* get block coordinate and instance coordinate, try to setup * device_rr_gsb */ if (type == "sb") { diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/fabric/read_xml_unique_blocks.h index c2e3a06cd..b1885fca7 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.h +++ b/openfpga/src/fabric/read_xml_unique_blocks.h @@ -30,10 +30,15 @@ *******************************************************************/ namespace openfpga { -vtr::Point read_xml_unique_instance_info( - pugi::xml_node& xml_instance_info, const pugiutil::loc_data& loc_data); +std::vector> read_xml_unique_instance_coords( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data); + +vtr::Point read_xml_unique_block_coord( + const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data); + void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, bool verbose_output); + int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output); } // namespace openfpga From 352c9b49c9c12ccbb37edea3c90a46b79f297d3d Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 28 Aug 2024 17:52:34 +0800 Subject: [PATCH 24/50] add cmd dependency --- openfpga/src/base/openfpga_setup_command_template.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index f73e3e01d..f4125a07a 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1269,15 +1269,21 @@ void add_setup_command_templates(openfpga::Shell& shell, /******************************** * Command 'read_unique_blocks' */ + std::vector cmd_dependency_read_unique_blocks_command; + cmd_dependency_read_unique_blocks_command.push_back( + link_arch_cmd_id); add_read_unique_blocks_command_template( - shell, openfpga_setup_cmd_class, std::vector(), + shell, openfpga_setup_cmd_class, cmd_dependency_read_unique_blocks_command, hidden); /******************************** * Command 'write_unique_blocks' */ + std::vector cmd_dependency_write_unique_blocks_command; + cmd_dependency_write_unique_blocks_command.push_back( + build_fabric_cmd_id); add_write_unique_blocks_command_template( - shell, openfpga_setup_cmd_class, std::vector(), + shell, openfpga_setup_cmd_class, cmd_dependency_write_unique_blocks_command, hidden); } } /* end namespace openfpga */ From a23860a6a7c8a8e3d152115c1924027be2e01cc8 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 28 Aug 2024 17:58:15 +0800 Subject: [PATCH 25/50] reformat code --- openfpga/src/base/openfpga_setup_command_template.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index f4125a07a..2aa8adae3 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1270,8 +1270,7 @@ void add_setup_command_templates(openfpga::Shell& shell, * Command 'read_unique_blocks' */ std::vector cmd_dependency_read_unique_blocks_command; - cmd_dependency_read_unique_blocks_command.push_back( - link_arch_cmd_id); + cmd_dependency_read_unique_blocks_command.push_back(link_arch_cmd_id); add_read_unique_blocks_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_read_unique_blocks_command, hidden); @@ -1280,8 +1279,7 @@ void add_setup_command_templates(openfpga::Shell& shell, * Command 'write_unique_blocks' */ std::vector cmd_dependency_write_unique_blocks_command; - cmd_dependency_write_unique_blocks_command.push_back( - build_fabric_cmd_id); + cmd_dependency_write_unique_blocks_command.push_back(build_fabric_cmd_id); add_write_unique_blocks_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_write_unique_blocks_command, hidden); From 8372eead6a81ab3053521898a4da080745777f6f Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 28 Aug 2024 18:14:33 +0800 Subject: [PATCH 26/50] add preload flag to device_rr_gsb and revert change to build fabric --- openfpga/src/annotation/device_rr_gsb.cpp | 5 +++++ openfpga/src/annotation/device_rr_gsb.h | 6 +++++- openfpga/src/base/openfpga_build_fabric_template.h | 5 ++--- openfpga/src/base/openfpga_setup_command_template.h | 5 ----- openfpga/src/fabric/read_xml_unique_blocks.cpp | 1 + .../read_unique_blocks_example_script.openfpga | 2 +- 6 files changed, 14 insertions(+), 10 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 33193d000..732df18bc 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -66,6 +66,9 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const { } } +void DeviceRRGSB::init_preload_flag() { preload_ = false; } +void DeviceRRGSB::set_preload_flag(const bool flag) { preload_ = flag; } +bool DeviceRRGSB::get_preload_flag() const { return preload_; } /* Identify if a GSB actually exists at a location */ bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph, const vtr::Point coord) const { @@ -420,6 +423,7 @@ void DeviceRRGSB::clear() { clear_sb_unique_module(); clear_sb_unique_module_id(); + init_preload_flag(); } void DeviceRRGSB::clear_unique_modules() { @@ -432,6 +436,7 @@ void DeviceRRGSB::clear_unique_modules() { clear_sb_unique_module(); clear_sb_unique_module_id(); + init_preload_flag(); } void DeviceRRGSB::clear_gsb() { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index f9a151f05..bd1178421 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -68,7 +68,9 @@ class DeviceRRGSB { size_t get_cb_unique_module_index(const t_rr_type& cb_type, const vtr::Point& coordinate) const; - public: /* Mutators */ + public: /* Mutators */ + void set_preload_flag(const bool flag); + bool get_preload_flag() const; void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ @@ -124,6 +126,7 @@ class DeviceRRGSB { private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ + void init_preload_flag(); void clear_cb_unique_module_id( const t_rr_type& cb_type); /* clean the content */ void clear_sb_unique_module(); /* clean the content */ @@ -162,6 +165,7 @@ class DeviceRRGSB { private: /* Internal Data */ std::vector> rr_gsb_; + bool preload_; std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 18825759e..c4303b962 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -102,7 +102,6 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_frame_view = cmd.option("frame_view"); CommandOptionId opt_compress_routing = cmd.option("compress_routing"); - CommandOptionId opt_preload = cmd.option("preload_unique_blocks"); CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin"); CommandOptionId opt_gen_random_fabric_key = cmd.option("generate_random_fabric_key"); @@ -146,13 +145,13 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, } if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - false == cmd_context.option_enable(cmd, opt_preload)) { + false == openfpga_ctx.device_rr_gsb().get_preload_flag()) { compress_routing_hierarchy_template( openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } else if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - true == cmd_context.option_enable(cmd, opt_preload)) { + true == openfpga_ctx.device_rr_gsb().get_preload_flag()) { openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 2aa8adae3..f13c62700 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -391,11 +391,6 @@ ShellCommandId add_build_fabric_command_template( "Compress the number of unique routing modules by " "identifying the unique GSBs"); - /* Add an option '--preload_unique_blocks' */ - shell_cmd.add_option( - "preload_unique_blocks", false, - "preload unique routing modules from user input xml file"); - /* Add an option '--duplicate_grid_pin' */ shell_cmd.add_option("duplicate_grid_pin", false, "Duplicate the pins on the same side of a grid"); diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp index 0888e390c..16c55a810 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.cpp +++ b/openfpga/src/fabric/read_xml_unique_blocks.cpp @@ -155,6 +155,7 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, /* As preloading gsb hasn't been developed, we should build gsb using the * preloaded cbs and sbs*/ device_rr_gsb.build_gsb_unique_module(); + device_rr_gsb.set_preload_flag(true); if (verbose_output) { report_unique_module_status_read(device_rr_gsb, true); } diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga index 491cefa4b..91e717186 100644 --- a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_example_script.openfpga @@ -21,7 +21,7 @@ read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml # Build the module graph # - Enabled compression on routing architecture modules # - Enable pin duplication on grid modules -build_fabric --compress_routing --preload_unique_blocks #--verbose +build_fabric --compress_routing #--verbose #write unique blocks xml file write_unique_blocks --file ./write_unique_block.xml --verbose --type xml From 643e3a2dd178d1e3259895bd190a75e473899d95 Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 29 Aug 2024 10:29:26 +0800 Subject: [PATCH 27/50] fix build bug --- openfpga/src/fabric/read_xml_unique_blocks.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/fabric/read_xml_unique_blocks.cpp index 16c55a810..0e59a9a4b 100644 --- a/openfpga/src/fabric/read_xml_unique_blocks.cpp +++ b/openfpga/src/fabric/read_xml_unique_blocks.cpp @@ -146,7 +146,7 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, } else { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_block_info), - "Invalid block type '%s'\n", type); + "Invalid block type '%s'\n", type.c_str()); } } else { bad_tag(xml_block_info, loc_data, xml_root, {"block"}); From 9e491680e6dee3ed44227031f4a2e1be33503c65 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 11:02:09 +0800 Subject: [PATCH 28/50] change file location --- openfpga/src/annotation/device_rr_gsb.h | 2 +- openfpga/src/{fabric => annotation}/read_xml_unique_blocks.cpp | 0 openfpga/src/{fabric => annotation}/read_xml_unique_blocks.h | 0 openfpga/src/{fabric => annotation}/write_xml_unique_blocks.cpp | 0 openfpga/src/{fabric => annotation}/write_xml_unique_blocks.h | 0 openfpga/src/base/openfpga_build_fabric_template.h | 1 + 6 files changed, 2 insertions(+), 1 deletion(-) rename openfpga/src/{fabric => annotation}/read_xml_unique_blocks.cpp (100%) rename openfpga/src/{fabric => annotation}/read_xml_unique_blocks.h (100%) rename openfpga/src/{fabric => annotation}/write_xml_unique_blocks.cpp (100%) rename openfpga/src/{fabric => annotation}/write_xml_unique_blocks.h (100%) diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index bd1178421..8b631107c 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -165,7 +165,7 @@ class DeviceRRGSB { private: /* Internal Data */ std::vector> rr_gsb_; - bool preload_; + bool preload_; // is_valid std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/fabric/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp similarity index 100% rename from openfpga/src/fabric/read_xml_unique_blocks.cpp rename to openfpga/src/annotation/read_xml_unique_blocks.cpp diff --git a/openfpga/src/fabric/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h similarity index 100% rename from openfpga/src/fabric/read_xml_unique_blocks.h rename to openfpga/src/annotation/read_xml_unique_blocks.h diff --git a/openfpga/src/fabric/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp similarity index 100% rename from openfpga/src/fabric/write_xml_unique_blocks.cpp rename to openfpga/src/annotation/write_xml_unique_blocks.cpp diff --git a/openfpga/src/fabric/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h similarity index 100% rename from openfpga/src/fabric/write_xml_unique_blocks.h rename to openfpga/src/annotation/write_xml_unique_blocks.h diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index c4303b962..9e94c9f2e 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -523,6 +523,7 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write unique blocks to a file */ + /* add check flag */ if (file_type == "xml") { return write_xml_unique_blocks(openfpga_ctx.device_rr_gsb(), file_name.c_str(), From cb003f88337b62f0e05d08ecc42b00ebd6b1d1a0 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 12:51:56 +0800 Subject: [PATCH 29/50] mod prelod flag --- openfpga/src/annotation/device_rr_gsb.cpp | 11 ++++++----- openfpga/src/annotation/device_rr_gsb.h | 8 ++++---- openfpga/src/annotation/read_xml_unique_blocks.cpp | 2 +- openfpga/src/annotation/write_xml_unique_blocks.cpp | 4 ++++ openfpga/src/base/openfpga_build_fabric_template.h | 2 +- openfpga/src/base/openfpga_setup_command_template.h | 5 +---- 6 files changed, 17 insertions(+), 15 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 732df18bc..a37921e7c 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -66,9 +66,9 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const { } } -void DeviceRRGSB::init_preload_flag() { preload_ = false; } -void DeviceRRGSB::set_preload_flag(const bool flag) { preload_ = flag; } -bool DeviceRRGSB::get_preload_flag() const { return preload_; } +void DeviceRRGSB::init_is_dirty_flag() { is_dirty_ = false; } +void DeviceRRGSB::set_is_dirty_flag(const bool flag) { is_dirty_ = flag; } +bool DeviceRRGSB::get_is_dirty_flag() const { return is_dirty_; } /* Identify if a GSB actually exists at a location */ bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph, const vtr::Point coord) const { @@ -363,6 +363,7 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANY); build_gsb_unique_module(); + set_is_dirty_flag(true); } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { @@ -423,7 +424,7 @@ void DeviceRRGSB::clear() { clear_sb_unique_module(); clear_sb_unique_module_id(); - init_preload_flag(); + init_is_dirty_flag(); } void DeviceRRGSB::clear_unique_modules() { @@ -436,7 +437,7 @@ void DeviceRRGSB::clear_unique_modules() { clear_sb_unique_module(); clear_sb_unique_module_id(); - init_preload_flag(); + init_is_dirty_flag(); } void DeviceRRGSB::clear_gsb() { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 8b631107c..43627fb9e 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -69,8 +69,8 @@ class DeviceRRGSB { const vtr::Point& coordinate) const; public: /* Mutators */ - void set_preload_flag(const bool flag); - bool get_preload_flag() const; + void set_is_dirty_flag(const bool flag); + bool get_is_dirty_flag() const; void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ @@ -126,7 +126,7 @@ class DeviceRRGSB { private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ - void init_preload_flag(); + void init_is_dirty_flag(); void clear_cb_unique_module_id( const t_rr_type& cb_type); /* clean the content */ void clear_sb_unique_module(); /* clean the content */ @@ -165,7 +165,7 @@ class DeviceRRGSB { private: /* Internal Data */ std::vector> rr_gsb_; - bool preload_; // is_valid + bool is_dirty_ = false; // is_valid std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 0e59a9a4b..9cb932c3e 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -155,7 +155,7 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, /* As preloading gsb hasn't been developed, we should build gsb using the * preloaded cbs and sbs*/ device_rr_gsb.build_gsb_unique_module(); - device_rr_gsb.set_preload_flag(true); + device_rr_gsb.set_is_dirty_flag(true); if (verbose_output) { report_unique_module_status_read(device_rr_gsb, true); } diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index 563755526..c664d6760 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -123,6 +123,10 @@ void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { vtr::ScopedStartFinishTimer timer("Write unique blocks..."); + if (device_rr_gsb.get_is_dirty_flag() == false) { + VTR_LOG_ERROR("unique_blocks are empty!"); + return CMD_EXEC_FATAL_ERROR; + } /* Create a file handler */ std::fstream fp; /* Open the file stream */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 9e94c9f2e..283171984 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -145,7 +145,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, } if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - false == openfpga_ctx.device_rr_gsb().get_preload_flag()) { + false == openfpga_ctx.device_rr_gsb().get_is_dirty_flag()) { compress_routing_hierarchy_template( openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index f13c62700..7ebaad845 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1273,11 +1273,8 @@ void add_setup_command_templates(openfpga::Shell& shell, /******************************** * Command 'write_unique_blocks' */ - std::vector cmd_dependency_write_unique_blocks_command; - cmd_dependency_write_unique_blocks_command.push_back(build_fabric_cmd_id); add_write_unique_blocks_command_template( - shell, openfpga_setup_cmd_class, cmd_dependency_write_unique_blocks_command, - hidden); + shell, openfpga_setup_cmd_class, std::vector(), hidden); } } /* end namespace openfpga */ From adeb9ba7ea8848172e3668033e307f4b7962072e Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 12:55:44 +0800 Subject: [PATCH 30/50] fix typo --- openfpga/src/base/openfpga_build_fabric_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 283171984..b39f356ea 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -151,7 +151,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } else if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - true == openfpga_ctx.device_rr_gsb().get_preload_flag()) { + true == openfpga_ctx.device_rr_gsb().get_is_dirty_flag()) { openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } From acce64058c469d7579ca0d51297b5e86f43fdb6f Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 14:17:42 +0800 Subject: [PATCH 31/50] add test case --- ...e_blocks_full_flow_example_script.openfpga | 79 ++++++++++++++++ ...e_blocks_full_flow_example_script.openfpga | 80 ++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 3 + .../config/task.conf | 42 +++++++++ .../config/tile_config.xml | 1 + .../read_unique_block.xml | 92 +++++++++++++++++++ .../config/task.conf | 41 +++++++++ .../config/tile_config.xml | 1 + 8 files changed, 339 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml diff --git a/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..a6f980f92 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,79 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# preload unique blocks from the provided xml file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..5de0100c1 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,80 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +#write unique blocks xml file +write_unique_blocks --file ./write_unique_block.xml --verbose --type xml + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 18994424d..1b9bf4bb1 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -21,6 +21,9 @@ run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@ echo -e "Testing preloading unique blocks" run-task basic_tests/preload_unique_blocks/write_unique_blocks $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ +run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@ +run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@ + echo -e "Testing testbenches using fpga core wrapper" run-task basic_tests/full_testbench/fpga_core_wrapper $@ diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf new file mode 100644 index 000000000..5ab911a8b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml new file mode 100644 index 000000000..12570d65e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf new file mode 100644 index 000000000..88dacdc64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks_full_flow/config/tile_config.xml @@ -0,0 +1 @@ + From 1d35a17a8b84cc4c65a1f9e662f9899fdee887f4 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 14:18:59 +0800 Subject: [PATCH 32/50] delete redundant file --- .../write_unique_blocks/design_variables.yml | 1 - 1 file changed, 1 deletion(-) delete mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml deleted file mode 100644 index de1dbf341..000000000 --- a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/write_unique_blocks/design_variables.yml +++ /dev/null @@ -1 +0,0 @@ -TEST_VARIABLE: 100 \ No newline at end of file From 94309c2a73407ab2ccc0f5cc1d7cdee099b53e20 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 15:33:47 +0800 Subject: [PATCH 33/50] change to reference --- openfpga/src/annotation/device_rr_gsb.cpp | 12 ++++++------ openfpga/src/annotation/device_rr_gsb.h | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index a37921e7c..ef2403c01 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -582,8 +582,8 @@ size_t DeviceRRGSB::get_cb_unique_module_index( } void DeviceRRGSB::preload_unique_cbx_module( - const vtr::Point block_coordinate, - const std::vector> instance_coords) { + const vtr::Point& block_coordinate, + const std::vector>& instance_coords) { /*check whether the preloaded value exceeds the limit */ size_t limit_x = cbx_unique_module_id_.size(); size_t limit_y = cbx_unique_module_id_[0].size(); @@ -606,8 +606,8 @@ void DeviceRRGSB::preload_unique_cbx_module( } void DeviceRRGSB::preload_unique_cby_module( - const vtr::Point block_coordinate, - const std::vector> instance_coords) { + const vtr::Point& block_coordinate, + const std::vector>& instance_coords) { /*check whether the preloaded value exceeds the limit */ size_t limit_x = cby_unique_module_id_.size(); size_t limit_y = cby_unique_module_id_[0].size(); @@ -631,8 +631,8 @@ void DeviceRRGSB::preload_unique_cby_module( } void DeviceRRGSB::preload_unique_sb_module( - const vtr::Point block_coordinate, - const std::vector> instance_coords) { + const vtr::Point& block_coordinate, + const std::vector>& instance_coords) { /*check whether the preloaded value exceeds the limit */ VTR_ASSERT(block_coordinate.x() < sb_unique_module_id_.size()); VTR_ASSERT(block_coordinate.y() < sb_unique_module_id_[0].size()); diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 43627fb9e..106bac82e 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -101,14 +101,14 @@ class DeviceRRGSB { of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ void preload_unique_cbx_module( - const vtr::Point block_coordinate, - const std::vector> instance_coords); + const vtr::Point& block_coordinate, + const std::vector>& instance_coords); void preload_unique_cby_module( - const vtr::Point block_coordinate, - const std::vector> instance_coords); + const vtr::Point& block_coordinate, + const std::vector>& instance_coords); void preload_unique_sb_module( - const vtr::Point block_coordinate, - const std::vector> instance_coords); + const vtr::Point& block_coordinate, + const std::vector>& instance_coords); void clear_unique_modules(); void get_id_sb_instance_map( std::map>>& id_instance_map) const; From a2b290c83b57b942efe738e8b1a937b6b0235db9 Mon Sep 17 00:00:00 2001 From: Lin Date: Fri, 30 Aug 2024 15:47:29 +0800 Subject: [PATCH 34/50] mod typo --- openfpga/src/base/openfpga_setup_command_template.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 7ebaad845..644facdb6 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -998,7 +998,7 @@ ShellCommandId add_write_unique_blocks_command_template( /* Add command 'compact_routing_hierarchy' to the Shell */ ShellCommandId shell_cmd_id = - shell.add_command(shell_cmd, "Preload unique blocks from xml file", hidden); + shell.add_command(shell_cmd, "Write unique blocks to a xml file", hidden); shell.set_command_class(shell_cmd_id, cmd_class_id); shell.set_command_execute_function(shell_cmd_id, write_unique_blocks_template); From a70582c6c4ac23e841383ff59e6f76b4f1af380a Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 4 Sep 2024 14:45:41 +0800 Subject: [PATCH 35/50] preload document copied --- .../manual/file_formats/unique_blocks.rst | 299 ++++++++++++++++++ 1 file changed, 299 insertions(+) create mode 100644 docs/source/manual/file_formats/unique_blocks.rst diff --git a/docs/source/manual/file_formats/unique_blocks.rst b/docs/source/manual/file_formats/unique_blocks.rst new file mode 100644 index 000000000..e35c8d844 --- /dev/null +++ b/docs/source/manual/file_formats/unique_blocks.rst @@ -0,0 +1,299 @@ +.. _file_formats_fabric_key: + +Fabric Key (.xml) +~~~~~~~~~~~~~~~~~ + +A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable blocks in the top-level FPGA fabric. + +Configurable Module +^^^^^^^^^^^^^^^^^^^ + +Fabric key can be applied to various modules. Each module can be a top-level FPGA fabric, or a submodule of the FPGA fabric. + +.. option:: + + Under each module, a set of keys can be defined. Note that for the top-level FPGA fabric, not only keys but also regions and shift-register banks can be defined. For non-top-level module, only keys are allowed. + + - ``name`` indicates the unique name of a valid module in FPGA fabric. Note that ``fpga_top`` is the considered as the module name of the top-level FPGA fabric. + + .. note:: ``fpga_core`` is not applicable to fabric key. + +Configurable Region +^^^^^^^^^^^^^^^^^^^ + +The top-level FPGA fabric can consist of several configurable regions, where a region may contain one or multiple configurable blocks. Each configurable region can be configured independently and in parrallel. + +.. option:: + + - ``id`` indicates the unique id of a configurable region in the fabric. + + .. warning:: The id must start from zero! + + .. note:: The number of regions defined in the fabric key must be consistent with the number of regions defined in the configuration protocol of architecture description. (See details in :ref:`config_protocol`). + +The following example shows how to define multiple configuration regions in the fabric key. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Configurable Block +^^^^^^^^^^^^^^^^^^^ + +Each configurable block is defined as a key. There are two ways to define a key, either with alias or with name and value. + +.. option:: + + - ``id`` indicates the sequence of the configurable memory block in the top-level FPGA fabric. + + - ``name`` indicates the module name of the configurable memory block. This property becomes optional when ``alias`` is defined. + + - ``value`` indicates the instance id of the configurable memory block in the top-level FPGA fabric. This property becomes optional when ``alias`` is defined. + + - ``alias`` indicates the instance name of the configurable memory block in the top-level FPGA fabric. If a valid alias is specified, the ``name`` and ``value`` are not required. + + - ``column`` indicates the relative x coordinate for a configurable memory in a configurable region at the top-level FPGA fabric. This is required when the memory bank protocol is selection. + + .. note:: The configurable memory blocks in the same column will share the same Bit Line (BL) bus + + - ``row`` indicates the relative y coordinate for a configurable memory in a configurable region at the top-level FPGA fabric. This is required when the memory bank protocol is selection. + + .. note:: The configurable memory blocks in the same row will share the same Word Line (WL) bus + +.. warning:: For fast loading of fabric key, strongly recommend to use pairs ``name`` and ``alias`` or ``name`` and ``value`` in the fabric key file. Using only ``alias`` may cause long parsing time for fabric key. + +The following is an example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. +This key contains only ``alias`` which is easy to craft. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. +This key contains only ``name`` and ``value`` which is fast to parse. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA using memory bank. +This key contains only ``name``, ``value``, ``row`` and ``column``. + +.. code-block:: xml + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +BL Shift Register Banks +^^^^^^^^^^^^^^^^^^^^^^^ + +.. note:: The customizable is only available when the shift-register-based memory bank is selected in :ref:`config_protocol` + +Each Bit-Line (BL) shift register bank is defined in the code block ````. +A shift register bank may contain multiple shift register chains. +- each shift register chain can be defined using the ``bank`` syntax +- the BLs controlled by each chain can be customized through the ``range`` syntax. + +.. option:: + + - ``id`` indicates the sequence of the shift register chain in the bank. The id denotes the index in the head or tail bus. For example, ``id="0"`` means the head or tail of the shift register will be in the first bit of a head bus ``head[0:4]`` + + - ``range`` indicates ``BL`` port to be controlled by this shift register chain. Multiple BL ports can be defined but the sequence matters. For example, ``bl[0:3], bl[6:10]`` infers a 9-bit shift register chain whose output ports are connected from ``bl[0]`` to ``bl[10]``. + + .. note:: When creating the range, you must know the number of BLs in the configuration region + + .. note:: ports must use ``bl`` as the reserved port name + + +WL Shift Register Banks +^^^^^^^^^^^^^^^^^^^^^^^ + +.. note:: The customizable is only available when the shift-register-based memory bank is selected in :ref:`config_protocol` + +Each Word-Line (WL) shift register bank is defined in the code block ````. +A shift register bank may contain multiple shift register chains. +- each shift register chain can be defined using the ``bank`` syntax +- the BLs controlled by each chain can be customized through the ``range`` syntax. + + +.. option:: + + - ``id`` indicates the sequence of the shift register chain in the bank. The id denotes the index in the head or tail bus. For example, ``id="0"`` means the head or tail of the shift register will be in the first bit of a head bus ``head[0:4]`` + + - ``range`` indicates ``WL`` port to be controlled by this shift register chain. Multiple WL ports can be defined but the sequence matters. For example, ``wl[0:3], wl[6:10]`` infers a 9-bit shift register chain whose output ports are connected from ``wl[0]`` to ``wl[10]``. + + .. note:: When creating the range, you must know the number of BLs in the configuration region + + .. note:: ports must use ``wl`` as the reserved port name + From 263eb6b7fb70c3f34e75813dced6281afa297f5b Mon Sep 17 00:00:00 2001 From: Jingrong Lin <145083116+treelin611@users.noreply.github.com> Date: Wed, 4 Sep 2024 15:14:41 +0800 Subject: [PATCH 36/50] Update unique_blocks.rst --- .../manual/file_formats/unique_blocks.rst | 317 +++--------------- 1 file changed, 40 insertions(+), 277 deletions(-) diff --git a/docs/source/manual/file_formats/unique_blocks.rst b/docs/source/manual/file_formats/unique_blocks.rst index e35c8d844..0445de969 100644 --- a/docs/source/manual/file_formats/unique_blocks.rst +++ b/docs/source/manual/file_formats/unique_blocks.rst @@ -1,299 +1,62 @@ -.. _file_formats_fabric_key: +.. _file_formats_unique_blocks: -Fabric Key (.xml) +Unique Blocks (.xml) ~~~~~~~~~~~~~~~~~ -A fabric key follows an XML format. As shown in the following XML code, the key file includes the organization of configurable blocks in the top-level FPGA fabric. - -Configurable Module -^^^^^^^^^^^^^^^^^^^ - -Fabric key can be applied to various modules. Each module can be a top-level FPGA fabric, or a submodule of the FPGA fabric. - -.. option:: - - Under each module, a set of keys can be defined. Note that for the top-level FPGA fabric, not only keys but also regions and shift-register banks can be defined. For non-top-level module, only keys are allowed. - - - ``name`` indicates the unique name of a valid module in FPGA fabric. Note that ``fpga_top`` is the considered as the module name of the top-level FPGA fabric. - - .. note:: ``fpga_core`` is not applicable to fabric key. - -Configurable Region -^^^^^^^^^^^^^^^^^^^ - -The top-level FPGA fabric can consist of several configurable regions, where a region may contain one or multiple configurable blocks. Each configurable region can be configured independently and in parrallel. - -.. option:: - - - ``id`` indicates the unique id of a configurable region in the fabric. - - .. warning:: The id must start from zero! - - .. note:: The number of regions defined in the fabric key must be consistent with the number of regions defined in the configuration protocol of architecture description. (See details in :ref:`config_protocol`). - -The following example shows how to define multiple configuration regions in the fabric key. - -.. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +A unique blocks file is formatted in XML. The unique blocks can be of type ``cbx``, ``cby`` or ``sb``. As illustrated by the XML code below, the file includes the type and coordinates of these unique blocks, as well as the coordinates of their corresponding instances. Configurable Block ^^^^^^^^^^^^^^^^^^^ -Each configurable block is defined as a key. There are two ways to define a key, either with alias or with name and value. +Unique blocks can be applied to various blocks, each of which can be of type ``cbx``, ``cby`` or ``sb``, and may have different coordinates. -.. option:: +.. option:: - - ``id`` indicates the sequence of the configurable memory block in the top-level FPGA fabric. + For each block, a set of keys can be defined. For unique blocks, both keys and instances can be specified. However, if a unique block does not have an instance, only keys are permitted. + + - ``type`` specifies the type of the unique block in the FPGA fabric. Valid values for ``type`` are ``cbx``, ``cby`` or ``sb``. - - ``name`` indicates the module name of the configurable memory block. This property becomes optional when ``alias`` is defined. + - ``x`` represents the x-coordinate of the unique block. - - ``value`` indicates the instance id of the configurable memory block in the top-level FPGA fabric. This property becomes optional when ``alias`` is defined. + - ``y`` represents the y-coordinate of the unique block. - - ``alias`` indicates the instance name of the configurable memory block in the top-level FPGA fabric. If a valid alias is specified, the ``name`` and ``value`` are not required. +Configurable Instance +^^^^^^^^^^^^^^^^^^^ - - ``column`` indicates the relative x coordinate for a configurable memory in a configurable region at the top-level FPGA fabric. This is required when the memory bank protocol is selection. +A specific unique block can have multiple instances, where each instance is a mirrored version of the unique block. Each instance shares the same type as its parent block and includes information about its coordinates. - .. note:: The configurable memory blocks in the same column will share the same Bit Line (BL) bus +.. option:: - - ``row`` indicates the relative y coordinate for a configurable memory in a configurable region at the top-level FPGA fabric. This is required when the memory bank protocol is selection. + - ``x`` specifies the x-coordinate of the instance. - .. note:: The configurable memory blocks in the same row will share the same Word Line (WL) bus + - ``y`` specifies the y-coordinate of the instance. -.. warning:: For fast loading of fabric key, strongly recommend to use pairs ``name`` and ``alias`` or ``name`` and ``value`` in the fabric key file. Using only ``alias`` may cause long parsing time for fabric key. -The following is an example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. -This key contains only ``alias`` which is easy to craft. +The following content provides an example of a unique block file: .. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA. -This key contains only ``name`` and ``value`` which is fast to parse. - -.. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -The following shows another example of a fabric key generate by OpenFPGA for a 2 :math:`\times` 2 FPGA using memory bank. -This key contains only ``name``, ``value``, ``row`` and ``column``. - -.. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -BL Shift Register Banks -^^^^^^^^^^^^^^^^^^^^^^^ - -.. note:: The customizable is only available when the shift-register-based memory bank is selected in :ref:`config_protocol` - -Each Bit-Line (BL) shift register bank is defined in the code block ````. -A shift register bank may contain multiple shift register chains. -- each shift register chain can be defined using the ``bank`` syntax -- the BLs controlled by each chain can be customized through the ``range`` syntax. - -.. option:: - - - ``id`` indicates the sequence of the shift register chain in the bank. The id denotes the index in the head or tail bus. For example, ``id="0"`` means the head or tail of the shift register will be in the first bit of a head bus ``head[0:4]`` - - - ``range`` indicates ``BL`` port to be controlled by this shift register chain. Multiple BL ports can be defined but the sequence matters. For example, ``bl[0:3], bl[6:10]`` infers a 9-bit shift register chain whose output ports are connected from ``bl[0]`` to ``bl[10]``. - - .. note:: When creating the range, you must know the number of BLs in the configuration region - - .. note:: ports must use ``bl`` as the reserved port name + + + + + + + + + + + + + + + + + + + + + + + -WL Shift Register Banks -^^^^^^^^^^^^^^^^^^^^^^^ - -.. note:: The customizable is only available when the shift-register-based memory bank is selected in :ref:`config_protocol` - -Each Word-Line (WL) shift register bank is defined in the code block ````. -A shift register bank may contain multiple shift register chains. -- each shift register chain can be defined using the ``bank`` syntax -- the BLs controlled by each chain can be customized through the ``range`` syntax. - - -.. option:: - - - ``id`` indicates the sequence of the shift register chain in the bank. The id denotes the index in the head or tail bus. For example, ``id="0"`` means the head or tail of the shift register will be in the first bit of a head bus ``head[0:4]`` - - - ``range`` indicates ``WL`` port to be controlled by this shift register chain. Multiple WL ports can be defined but the sequence matters. For example, ``wl[0:3], wl[6:10]`` infers a 9-bit shift register chain whose output ports are connected from ``wl[0]`` to ``wl[10]``. - - .. note:: When creating the range, you must know the number of BLs in the configuration region - - .. note:: ports must use ``wl`` as the reserved port name - From af7201d4bb6eac71e0aedb6f5b3296386b7f7ff2 Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 9 Sep 2024 11:19:12 +0800 Subject: [PATCH 37/50] fix is_compressed_ tag --- openfpga/src/annotation/device_rr_gsb.cpp | 11 +++++------ openfpga/src/annotation/device_rr_gsb.h | 6 ++---- .../src/base/openfpga_build_fabric_template.h | 16 +++++++--------- 3 files changed, 14 insertions(+), 19 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index ef2403c01..07d608b1b 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -66,9 +66,8 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const { } } -void DeviceRRGSB::init_is_dirty_flag() { is_dirty_ = false; } -void DeviceRRGSB::set_is_dirty_flag(const bool flag) { is_dirty_ = flag; } -bool DeviceRRGSB::get_is_dirty_flag() const { return is_dirty_; } + +bool DeviceRRGSB::is_compressed() const { return is_compressed_; } /* Identify if a GSB actually exists at a location */ bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph, const vtr::Point coord) const { @@ -363,7 +362,7 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANY); build_gsb_unique_module(); - set_is_dirty_flag(true); + is_compressed_ = true; } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { @@ -424,7 +423,7 @@ void DeviceRRGSB::clear() { clear_sb_unique_module(); clear_sb_unique_module_id(); - init_is_dirty_flag(); + is_compressed_ = false; } void DeviceRRGSB::clear_unique_modules() { @@ -437,7 +436,7 @@ void DeviceRRGSB::clear_unique_modules() { clear_sb_unique_module(); clear_sb_unique_module_id(); - init_is_dirty_flag(); + is_compressed_ = false; } void DeviceRRGSB::clear_gsb() { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 106bac82e..ff3a604b1 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -69,8 +69,7 @@ class DeviceRRGSB { const vtr::Point& coordinate) const; public: /* Mutators */ - void set_is_dirty_flag(const bool flag); - bool get_is_dirty_flag() const; + bool is_compressed() const; void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ @@ -126,7 +125,6 @@ class DeviceRRGSB { private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ void clear_cb_unique_module(const t_rr_type& cb_type); /* clean the content */ - void init_is_dirty_flag(); void clear_cb_unique_module_id( const t_rr_type& cb_type); /* clean the content */ void clear_sb_unique_module(); /* clean the content */ @@ -165,7 +163,7 @@ class DeviceRRGSB { private: /* Internal Data */ std::vector> rr_gsb_; - bool is_dirty_ = false; // is_valid + bool is_compressed_ = false; // is_valid std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index b39f356ea..e5db102ed 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -125,11 +125,10 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, cmd.option_name(opt_duplicate_grid_pin).c_str()); return CMD_EXEC_FATAL_ERROR; } - if (!cmd_context.option_enable(cmd, opt_compress_routing)) { + if (!openfpga_ctx.device_rr_gsb().is_compressed()) { VTR_LOG_ERROR( - "Option '%s' requires options '%s' to be enabled due to a conflict!\n", - cmd.option_name(opt_group_tile).c_str(), - cmd.option_name(opt_compress_routing).c_str()); + "Option '%s' requires unique blocks to be valid due to a conflict!\n", + cmd.option_name(opt_group_tile).c_str()); return CMD_EXEC_FATAL_ERROR; } } @@ -145,13 +144,12 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, } if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - false == openfpga_ctx.device_rr_gsb().get_is_dirty_flag()) { + false == openfpga_ctx.device_rr_gsb().is_compressed()) { compress_routing_hierarchy_template( openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose)); /* Update flow manager to enable compress routing */ openfpga_ctx.mutable_flow_manager().set_compress_routing(true); - } else if (true == cmd_context.option_enable(cmd, opt_compress_routing) && - true == openfpga_ctx.device_rr_gsb().get_is_dirty_flag()) { + } else if (true == openfpga_ctx.device_rr_gsb().is_compressed()) { openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } @@ -180,7 +178,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, */ TileConfig tile_config; if (cmd_context.option_enable(cmd, opt_group_tile)) { - if (!cmd_context.option_enable(cmd, opt_compress_routing)) { + if (!openfpga_ctx.device_rr_gsb().is_compressed()) { VTR_LOG_ERROR( "Group tile is applicable only when compress routing is enabled!\n"); return CMD_EXEC_FATAL_ERROR; @@ -198,7 +196,7 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, openfpga_ctx.mutable_fabric_tile(), openfpga_ctx.mutable_module_name_map(), const_cast(openfpga_ctx), g_vpr_ctx.device(), cmd_context.option_enable(cmd, opt_frame_view), - cmd_context.option_enable(cmd, opt_compress_routing), + openfpga_ctx.device_rr_gsb().is_compressed(), cmd_context.option_enable(cmd, opt_duplicate_grid_pin), predefined_fabric_key, tile_config, cmd_context.option_enable(cmd, opt_group_config_block), From 41d0eb7736f148b220cef768007c0f29611c605b Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 9 Sep 2024 11:36:48 +0800 Subject: [PATCH 38/50] modification on device_rr_gsb --- openfpga/src/annotation/device_rr_gsb.cpp | 24 +++++++++---------- .../src/annotation/read_xml_unique_blocks.cpp | 4 +--- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 07d608b1b..fdf7b9a74 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -66,7 +66,6 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const { } } - bool DeviceRRGSB::is_compressed() const { return is_compressed_; } /* Identify if a GSB actually exists at a location */ bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph, @@ -173,16 +172,17 @@ void DeviceRRGSB::reserve(const vtr::Point& coordinate) { cby_unique_module_id_[x].resize(coordinate.y()); } } -void DeviceRRGSB::reserve_unique_modules(const vtr::Point& coordinate) { - sb_unique_module_id_.resize(coordinate.x()); - cbx_unique_module_id_.resize(coordinate.x()); - cby_unique_module_id_.resize(coordinate.x()); +void DeviceRRGSB::reserve_unique_modules() { + /* As rr_gsb_ has been built, it has valid size. Will reserve space for unique + * blocks according to rr_gsb_'s size*/ + sb_unique_module_id_.resize(rr_gsb_.x()); + cbx_unique_module_id_.resize(rr_gsb_.x()); + cby_unique_module_id_.resize(rr_gsb_.x()); - for (size_t x = 0; x < coordinate.x(); ++x) { - sb_unique_module_id_[x].resize(coordinate.y()); - - cbx_unique_module_id_[x].resize(coordinate.y()); - cby_unique_module_id_[x].resize(coordinate.y()); + for (std::size_t i = 0; i < rr_gsb_.size(); ++i) { + sb_unique_module_id_[i].resize(rr_gsb_[i].size()); + cbx_unique_module_id_[i].resize(rr_gsb_[i].size()); + cby_unique_module_id_[i].resize(rr_gsb_[i].size()); } } @@ -353,6 +353,7 @@ void DeviceRRGSB::build_gsb_unique_module() { } } } + is_compressed_ = true; } void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { @@ -361,8 +362,7 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANX); build_cb_unique_module(rr_graph, CHANY); - build_gsb_unique_module(); - is_compressed_ = true; + build_gsb_unique_module(); /*is_compressed_ flip inside build_gsb_unique_module*/ } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 9cb932c3e..88a30280c 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -117,8 +117,7 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, pugi::xml_node xml_root = get_single_child(doc, "unique_blocks", loc_data); /* clear unique modules & reserve memory to relavant vectors */ device_rr_gsb.clear_unique_modules(); - vtr::Point grid_coord(g_vpr_ctx.device().grid.width() - 1, - g_vpr_ctx.device().grid.height() - 1); + // vtr::Point grid_coord(rr_gsb_.size()); device_rr_gsb.reserve_unique_modules(grid_coord); /* load unique blocks xml file and set up device_rr_gdb */ @@ -155,7 +154,6 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, /* As preloading gsb hasn't been developed, we should build gsb using the * preloaded cbs and sbs*/ device_rr_gsb.build_gsb_unique_module(); - device_rr_gsb.set_is_dirty_flag(true); if (verbose_output) { report_unique_module_status_read(device_rr_gsb, true); } From d15025d9d2c3c34cabefbe205e2312096088509c Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 9 Sep 2024 14:18:47 +0800 Subject: [PATCH 39/50] add a task case to ease the use of compress_routing option --- ...e_blocks_full_flow_example_script.openfpga | 82 +++++++++++++++++ .../regression_test_scripts/basic_reg_test.sh | 1 + .../read_write_unique_blocks/config/task.conf | 42 +++++++++ .../config/tile_config.xml | 1 + .../read_unique_block.xml | 92 +++++++++++++++++++ 5 files changed, 218 insertions(+) create mode 100644 openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml create mode 100644 openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml diff --git a/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga new file mode 100644 index 000000000..715478707 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga @@ -0,0 +1,82 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Optionally pb pin fixup +${OPENFPGA_PB_PIN_FIXUP_COMMAND} + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# preload unique blocks from the provided xml file +read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose + +#write unique blocks to a xml format file +write_unique_blocks --file ./write_unique_block.xml --verbose --type xml + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS} + +# Write the SDC files for PnR backend +# - Turn on every options here +# FIXME: Not supported yet. +#write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 1b9bf4bb1..aadc17f0c 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -23,6 +23,7 @@ run-task basic_tests/preload_unique_blocks/write_unique_blocks $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks $@ run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@ run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@ +run-task basic_tests/preload_unique_blocks/read_write_unique_blocks $@ echo -e "Testing testbenches using fpga core wrapper" diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf new file mode 100644 index 000000000..f7a3fab83 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_write_unique_blocks_full_flow_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml +openfpga_vpr_extra_options= +openfpga_pb_pin_fixup_command= +openfpga_vpr_device=4x4 +openfpga_vpr_route_chan_width=20 +openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml +openfpga_verilog_testbench_options=--explicit_port_mapping + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = or2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml new file mode 100644 index 000000000..1a1f3f6e8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/config/tile_config.xml @@ -0,0 +1 @@ + diff --git a/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml new file mode 100644 index 000000000..12570d65e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_write_unique_blocks/read_unique_block.xml @@ -0,0 +1,92 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From f1547bae8a23dd9d6d5cddf6ccbb8b12c0d44f5d Mon Sep 17 00:00:00 2001 From: Lin Date: Mon, 9 Sep 2024 18:18:07 +0800 Subject: [PATCH 40/50] fix build error --- openfpga/src/annotation/device_rr_gsb.cpp | 6 +++--- openfpga/src/annotation/device_rr_gsb.h | 4 +--- openfpga/src/annotation/read_xml_unique_blocks.cpp | 2 +- openfpga/src/annotation/write_xml_unique_blocks.cpp | 2 +- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index fdf7b9a74..d2eb8da29 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -175,9 +175,9 @@ void DeviceRRGSB::reserve(const vtr::Point& coordinate) { void DeviceRRGSB::reserve_unique_modules() { /* As rr_gsb_ has been built, it has valid size. Will reserve space for unique * blocks according to rr_gsb_'s size*/ - sb_unique_module_id_.resize(rr_gsb_.x()); - cbx_unique_module_id_.resize(rr_gsb_.x()); - cby_unique_module_id_.resize(rr_gsb_.x()); + sb_unique_module_id_.resize(rr_gsb_.size()); + cbx_unique_module_id_.resize(rr_gsb_.size()); + cby_unique_module_id_.resize(rr_gsb_.size()); for (std::size_t i = 0; i < rr_gsb_.size(); ++i) { sb_unique_module_id_[i].resize(rr_gsb_[i].size()); diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index ff3a604b1..03c99e6af 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -76,9 +76,7 @@ class DeviceRRGSB { void reserve( const vtr::Point& coordinate); /* Pre-allocate the rr_switch_block array that the device requires */ - void reserve_unique_modules( - const vtr::Point& - coordinate); /* Pre-allocate the rr_sb_unique_module_id matrix that the + void reserve_unique_modules(); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ void resize_upon_need( const vtr::Point& diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 88a30280c..8abcaf3cd 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -118,7 +118,7 @@ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, /* clear unique modules & reserve memory to relavant vectors */ device_rr_gsb.clear_unique_modules(); // vtr::Point grid_coord(rr_gsb_.size()); - device_rr_gsb.reserve_unique_modules(grid_coord); + device_rr_gsb.reserve_unique_modules(); /* load unique blocks xml file and set up device_rr_gdb */ for (pugi::xml_node xml_block_info : xml_root.children()) { diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index c664d6760..65c69e355 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -123,7 +123,7 @@ void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { vtr::ScopedStartFinishTimer timer("Write unique blocks..."); - if (device_rr_gsb.get_is_dirty_flag() == false) { + if (device_rr_gsb.is_compressed() == false) { VTR_LOG_ERROR("unique_blocks are empty!"); return CMD_EXEC_FATAL_ERROR; } From ae6a8cb60431c650a9f7ca4f8f1f937142a1f3ae Mon Sep 17 00:00:00 2001 From: Lin Date: Tue, 10 Sep 2024 14:34:42 +0800 Subject: [PATCH 41/50] fix bug --- openfpga/src/annotation/device_rr_gsb.cpp | 3 ++- openfpga/src/annotation/device_rr_gsb.h | 4 ++-- openfpga/src/base/openfpga_build_fabric_template.h | 14 ++++++++------ 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index d2eb8da29..c044ffebf 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -362,7 +362,8 @@ void DeviceRRGSB::build_unique_module(const RRGraphView& rr_graph) { build_cb_unique_module(rr_graph, CHANX); build_cb_unique_module(rr_graph, CHANY); - build_gsb_unique_module(); /*is_compressed_ flip inside build_gsb_unique_module*/ + build_gsb_unique_module(); /*is_compressed_ flip inside + build_gsb_unique_module*/ } void DeviceRRGSB::add_gsb_unique_module(const vtr::Point& coordinate) { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 03c99e6af..b042fe689 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -76,8 +76,8 @@ class DeviceRRGSB { void reserve( const vtr::Point& coordinate); /* Pre-allocate the rr_switch_block array that the device requires */ - void reserve_unique_modules(); /* Pre-allocate the rr_sb_unique_module_id matrix that the - device requires */ + void reserve_unique_modules(); /* Pre-allocate the rr_sb_unique_module_id + matrix that the device requires */ void resize_upon_need( const vtr::Point& coordinate); /* Resize the rr_switch_block array if needed */ diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index e5db102ed..554b1556e 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -125,12 +125,6 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, cmd.option_name(opt_duplicate_grid_pin).c_str()); return CMD_EXEC_FATAL_ERROR; } - if (!openfpga_ctx.device_rr_gsb().is_compressed()) { - VTR_LOG_ERROR( - "Option '%s' requires unique blocks to be valid due to a conflict!\n", - cmd.option_name(opt_group_tile).c_str()); - return CMD_EXEC_FATAL_ERROR; - } } /* Conflicts: duplicate_grid_pin does not support any port merge */ if (cmd_context.option_enable(cmd, opt_duplicate_grid_pin)) { @@ -153,6 +147,14 @@ int build_fabric_template(T& openfpga_ctx, const Command& cmd, openfpga_ctx.mutable_flow_manager().set_compress_routing(true); } + if (cmd_context.option_enable(cmd, opt_group_tile)) { + if (!openfpga_ctx.device_rr_gsb().is_compressed()) { + VTR_LOG_ERROR( + "Option '%s' requires unique blocks to be valid due to a conflict!\n", + cmd.option_name(opt_group_tile).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + } VTR_LOG("\n"); /* Record the execution status in curr_status for each command From b2a5bd84376c747b844aa57256d405a93238dffa Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 11 Sep 2024 14:35:24 +0800 Subject: [PATCH 42/50] fix merge error --- openfpga/src/base/openfpga_setup_command_template.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 61123dcff..eb534fcb7 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1016,11 +1016,11 @@ ShellCommandId add_write_unique_blocks_command_template( } - *******************************************************************/ + /****************************************************************** * - Add a command to Shell environment: report_reference * - Add associated options * - Add command dependency - *******************************************************************/ + ******************************************************************/ template ShellCommandId add_report_reference_command_template( openfpga::Shell& shell, const ShellCommandClassId& cmd_class_id, @@ -1320,7 +1320,6 @@ void add_setup_command_templates(openfpga::Shell& shell, cmd_dependency_report_reference.push_back(build_fabric_cmd_id); add_report_reference_command_template( shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden); -} /******************************** * Command 'read_unique_blocks' From 55611dbfe7937b57721501bf7bbf3600d9e86d68 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 11 Sep 2024 18:08:51 +0800 Subject: [PATCH 43/50] rewrite write_xml function --- openfpga/src/annotation/device_rr_gsb.cpp | 182 +++++++++--------- openfpga/src/annotation/device_rr_gsb.h | 27 ++- .../annotation/write_xml_unique_blocks.cpp | 117 ++++++----- .../src/annotation/write_xml_unique_blocks.h | 8 +- .../src/base/openfpga_build_fabric_template.h | 8 +- .../base/openfpga_setup_command_template.h | 5 +- 6 files changed, 179 insertions(+), 168 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index c044ffebf..ced7e6b9d 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -96,6 +96,80 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const { return sb_unique_module_.size(); } +vtr::Point DeviceRRGSB::get_sb_unique_block_coord(size_t id) const { + return sb_unique_module_[id]; +} + +std::vector> DeviceRRGSB::get_sb_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const { + auto unique_module_id = + sb_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + std::vector> instance_map; + for (size_t location_x = 0; location_x < sb_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < sb_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id_instance = + sb_unique_module_id_[location_x][location_y]; + if (unique_module_id_instance == unique_module_id) { + vtr::Point instance_coord(location_x, location_y); + instance_map.push_back(instance_coord); + } + } + } + return instance_map; +} + +vtr::Point DeviceRRGSB::get_cbx_unique_block_coord(size_t id) const { + return cbx_unique_module_[id]; +} + +std::vector> +DeviceRRGSB::get_cbx_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const { + auto unique_module_id = + cbx_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + std::vector> instance_map; + for (size_t location_x = 0; location_x < cbx_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < cbx_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id_instance = + cbx_unique_module_id_[location_x][location_y]; + if (unique_module_id_instance == unique_module_id) { + vtr::Point instance_coord(location_x, location_y); + instance_map.push_back(instance_coord); + } + } + } + return instance_map; +} + +vtr::Point DeviceRRGSB::get_cby_unique_block_coord(size_t id) const { + return cby_unique_module_[id]; +} + +std::vector> +DeviceRRGSB::get_cby_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const { + auto unique_module_id = + cby_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; + std::vector> instance_map; + for (size_t location_x = 0; location_x < cby_unique_module_id_.size(); + ++location_x) { + for (size_t location_y = 0; location_y < cby_unique_module_id_[0].size(); + ++location_y) { + auto unique_module_id_instance = + cby_unique_module_id_[location_x][location_y]; + if (unique_module_id_instance == unique_module_id) { + vtr::Point instance_coord(location_x, location_y); + instance_map.push_back(instance_coord); + } + } + } + return instance_map; +} + /* get the number of unique mirrors of switch blocks */ size_t DeviceRRGSB::get_num_gsb_unique_module() const { return gsb_unique_module_.size(); @@ -173,8 +247,8 @@ void DeviceRRGSB::reserve(const vtr::Point& coordinate) { } } void DeviceRRGSB::reserve_unique_modules() { - /* As rr_gsb_ has been built, it has valid size. Will reserve space for unique - * blocks according to rr_gsb_'s size*/ + /* As rr_gsb_ has been built, it has valid size. Will reserve space for + * unique blocks according to rr_gsb_'s size*/ sb_unique_module_id_.resize(rr_gsb_.size()); cbx_unique_module_id_.resize(rr_gsb_.size()); cby_unique_module_id_.resize(rr_gsb_.size()); @@ -206,8 +280,8 @@ void DeviceRRGSB::resize_upon_need(const vtr::Point& coordinate) { } } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ void DeviceRRGSB::add_rr_gsb(const vtr::Point& coordinate, const RRGSB& rr_gsb) { /* Resize upon needs*/ @@ -229,8 +303,8 @@ RRGSB& DeviceRRGSB::get_mutable_gsb(const size_t& x, const size_t& y) { return get_mutable_gsb(coordinate); } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, const t_rr_type& cb_type) { /* Make sure a clean start */ @@ -246,7 +320,8 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, continue; } - /* Traverse the unique_mirror list and check it is an mirror of another */ + /* Traverse the unique_mirror list and check it is an mirror of another + */ for (size_t id = 0; id < get_num_cb_unique_module(cb_type); ++id) { const RRGSB& unique_module = get_cb_unique_module(cb_type, id); if (true == is_cb_mirror(rr_graph, device_annotation_, rr_gsb_[ix][iy], @@ -269,8 +344,8 @@ void DeviceRRGSB::build_cb_unique_module(const RRGraphView& rr_graph, } } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) { /* Make sure a clean start */ clear_sb_unique_module(); @@ -281,7 +356,8 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) { bool is_unique_module = true; vtr::Point sb_coordinate(ix, iy); - /* Traverse the unique_mirror list and check it is an mirror of another */ + /* Traverse the unique_mirror list and check it is an mirror of another + */ for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { /* Check if the two modules have the same submodules, * if so, these two modules are the same, indicating the sb is not @@ -308,8 +384,8 @@ void DeviceRRGSB::build_sb_unique_module(const RRGraphView& rr_graph) { } } -/* Add a switch block to the array, which will automatically identify and update - * the lists of unique mirrors and rotatable mirrors */ +/* Add a switch block to the array, which will automatically identify and + * update the lists of unique mirrors and rotatable mirrors */ /* Find repeatable GSB block in the array */ void DeviceRRGSB::build_gsb_unique_module() { @@ -321,11 +397,12 @@ void DeviceRRGSB::build_gsb_unique_module() { bool is_unique_module = true; vtr::Point gsb_coordinate(ix, iy); - /* Traverse the unique_mirror list and check it is an mirror of another */ + /* Traverse the unique_mirror list and check it is an mirror of another + */ for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { /* We have alreay built sb and cb unique module list - * We just need to check if the unique module id of SBs, CBX and CBY are - * the same or not + * We just need to check if the unique module id of SBs, CBX and CBY + * are the same or not */ const vtr::Point& gsb_unique_module_coordinate = gsb_unique_module_[id]; @@ -650,79 +727,4 @@ void DeviceRRGSB::preload_unique_sb_module( sb_unique_module_id_[block_coordinate.x()][block_coordinate.y()]; } } - -/*The following four functions will allow us to get -The map between (id,mirror instance coord), (id, unique block coord) -As the unique block and its mirror instances share the same id, we can get the -map between (unique block coord, mirror instance coord) -*/ -void DeviceRRGSB::get_id_unique_sb_block_map( - std::map>& id_unique_block_map) const { - for (size_t id = 0; id < get_num_sb_unique_module(); ++id) { - const auto& unique_block_coord = sb_unique_module_[id]; - auto unique_module_id = - sb_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; - id_unique_block_map[unique_module_id] = unique_block_coord; - } -} - -void DeviceRRGSB::get_id_sb_instance_map( - std::map>>& id_instance_map) const { - for (size_t location_x = 0; location_x < sb_unique_module_id_.size(); - ++location_x) { - for (size_t location_y = 0; location_y < sb_unique_module_id_[0].size(); - ++location_y) { - auto unique_module_id = sb_unique_module_id_[location_x][location_y]; - vtr::Point instance_coord(location_x, location_y); - id_instance_map[unique_module_id].push_back(instance_coord); - } - } -} - -void DeviceRRGSB::get_id_unique_cbx_block_map( - std::map>& id_unique_block_map) const { - for (size_t id = 0; id < get_num_cb_unique_module(CHANX); ++id) { - const auto& unique_block_coord = cbx_unique_module_[id]; - auto unique_module_id = - cbx_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; - id_unique_block_map[unique_module_id] = unique_block_coord; - } -} - -void DeviceRRGSB::get_id_cbx_instance_map( - std::map>>& id_instance_map) const { - for (size_t location_x = 0; location_x < cbx_unique_module_id_.size(); - ++location_x) { - for (size_t location_y = 0; location_y < cbx_unique_module_id_[0].size(); - ++location_y) { - auto unique_module_id = cbx_unique_module_id_[location_x][location_y]; - vtr::Point instance_coord(location_x, location_y); - id_instance_map[unique_module_id].push_back(instance_coord); - } - } -} - -void DeviceRRGSB::get_id_unique_cby_block_map( - std::map>& id_unique_block_map) const { - for (size_t id = 0; id < get_num_cb_unique_module(CHANY); ++id) { - const auto& unique_block_coord = cby_unique_module_[id]; - auto unique_module_id = - cby_unique_module_id_[unique_block_coord.x()][unique_block_coord.y()]; - id_unique_block_map[unique_module_id] = unique_block_coord; - } -} - -void DeviceRRGSB::get_id_cby_instance_map( - std::map>>& id_instance_map) const { - for (size_t location_x = 0; location_x < cby_unique_module_id_.size(); - ++location_x) { - for (size_t location_y = 0; location_y < cby_unique_module_id_[0].size(); - ++location_y) { - auto unique_module_id = cby_unique_module_id_[location_x][location_y]; - vtr::Point instance_coord(location_x, location_y); - id_instance_map[unique_module_id].push_back(instance_coord); - } - } -} - } /* End namespace openfpga*/ diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index b042fe689..e40a81892 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -43,8 +43,19 @@ class DeviceRRGSB { const vtr::Point& coordinate) const; size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ - size_t get_num_sb_unique_module() - const; /* get the number of unique mirrors of switch blocks */ + + size_t get_num_sb_unique_module() const; + vtr::Point get_sb_unique_block_coord(size_t id) const; + std::vector> get_sb_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const; + + vtr::Point get_cbx_unique_block_coord(size_t id) const; + std::vector> get_cbx_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const; + vtr::Point get_cby_unique_block_coord(size_t id) const; + std::vector> get_cby_unique_block_instance_coord( + const vtr::Point& unique_block_coord) const; + const RRGSB& get_gsb_unique_module( const size_t& index) const; /* Get a rr-gsb which is a unique mirror */ const RRGSB& get_sb_unique_module(const size_t& index) @@ -107,18 +118,6 @@ class DeviceRRGSB { const vtr::Point& block_coordinate, const std::vector>& instance_coords); void clear_unique_modules(); - void get_id_sb_instance_map( - std::map>>& id_instance_map) const; - void get_id_unique_sb_block_map( - std::map>& id_unique_block_map) const; - void get_id_cbx_instance_map( - std::map>>& id_instance_map) const; - void get_id_unique_cbx_block_map( - std::map>& id_unique_block_map) const; - void get_id_cby_instance_map( - std::map>>& id_instance_map) const; - void get_id_unique_cby_block_map( - std::map>& id_unique_block_map) const; private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index 65c69e355..3550af531 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -32,45 +32,41 @@ * instance is the mirror of unique module. *******************************************************************/ namespace openfpga { - -int write_xml_block( - std::map>& id_unique_block_map, - std::map>>& id_instance_map, - std::fstream& fp, std::string type) { - /* Validate the file stream */ +int write_xml_atom_block(std::fstream& fp, + const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + std::string type) { if (false == openfpga::valid_file_stream(fp)) { return CMD_EXEC_FATAL_ERROR; } - for (const auto& pair : id_unique_block_map) { - openfpga::write_tab_to_file(fp, 1); - fp << "" - << "\n"; + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; - fp << "/>" - << "\n"; - } + for (const auto& instance_info : instance_map) { + if (instance_info.x() == unique_block_coord.x() && + instance_info.y() == unique_block_coord.y()) { + ; + } else { + openfpga::write_tab_to_file(fp, 2); + fp << "" + << "\n"; } - openfpga::write_tab_to_file(fp, 1); - fp << "" - << "\n"; } - - return CMD_EXEC_SUCCESS; + openfpga::write_tab_to_file(fp, 1); + fp << "" + << "\n"; + return openfpga::CMD_EXEC_SUCCESS; } void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, @@ -139,24 +135,45 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, fp << "" << "\n"; - int err_code = 0; - std::map> id_unique_block_map; - std::map>> id_instance_map; - device_rr_gsb.get_id_unique_sb_block_map(id_unique_block_map); - device_rr_gsb.get_id_sb_instance_map(id_instance_map); - err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "sb"); + for (size_t id = 0; id < device_rr_gsb.get_num_sb_unique_module(); ++id) { + const auto unique_block_coord = device_rr_gsb.get_sb_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_sb_unique_block_instance_coord(unique_block_coord); + int status_code = + write_xml_atom_block(fp, instance_map, unique_block_coord, "sb"); + if (status_code != 0) { + VTR_LOG_ERROR("write sb unique blocks into xml file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } - id_unique_block_map.clear(); - id_instance_map.clear(); - device_rr_gsb.get_id_unique_cbx_block_map(id_unique_block_map); - device_rr_gsb.get_id_cbx_instance_map(id_instance_map); - err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cbx"); + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANX); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cbx_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cbx_unique_block_instance_coord(unique_block_coord); + int status_code = + write_xml_atom_block(fp, instance_map, unique_block_coord, "cbx"); + if (status_code != 0) { + VTR_LOG_ERROR("write cbx unique blocks into xml file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } - id_unique_block_map.clear(); - id_instance_map.clear(); - device_rr_gsb.get_id_unique_cby_block_map(id_unique_block_map); - device_rr_gsb.get_id_cby_instance_map(id_instance_map); - err_code += write_xml_block(id_unique_block_map, id_instance_map, fp, "cby"); + for (size_t id = 0; id < device_rr_gsb.get_num_cb_unique_module(CHANY); + ++id) { + const auto unique_block_coord = + device_rr_gsb.get_cby_unique_block_coord(id); + const std::vector> instance_map = + device_rr_gsb.get_cby_unique_block_instance_coord(unique_block_coord); + int status_code = + write_xml_atom_block(fp, instance_map, unique_block_coord, "cby"); + if (status_code != 0) { + VTR_LOG_ERROR("write cby unique blocks into xml file failed!"); + return CMD_EXEC_FATAL_ERROR; + } + } /* Finish writing the root node */ fp << "" @@ -168,10 +185,6 @@ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, report_unique_module_status_write(device_rr_gsb, true); } - if (err_code >= 1) { - return CMD_EXEC_FATAL_ERROR; - } else { - return CMD_EXEC_SUCCESS; - } + return CMD_EXEC_SUCCESS; } } // namespace openfpga diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h index f8aa5959d..7eb8422ae 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.h +++ b/openfpga/src/annotation/write_xml_unique_blocks.h @@ -30,10 +30,10 @@ *******************************************************************/ namespace openfpga { -int write_xml_block( - std::map>& id_unique_block_map, - std::map>>& id_instance_map, - std::fstream& fp, std::string type); +int write_xml_atom_block(std::fstream& fp, + const std::vector>& instance_map, + const vtr::Point& unique_block_coord, + std::string type); void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, bool verbose_output); int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, diff --git a/openfpga/src/base/openfpga_build_fabric_template.h b/openfpga/src/base/openfpga_build_fabric_template.h index 88ed6a336..671b2043d 100644 --- a/openfpga/src/base/openfpga_build_fabric_template.h +++ b/openfpga/src/base/openfpga_build_fabric_template.h @@ -479,15 +479,14 @@ int write_fabric_pin_physical_location_template( cmd_context.option_enable(cmd, opt_verbose)); } - template int read_unique_blocks_template(T& openfpga_ctx, const Command& cmd, const CommandContext& cmd_context) { CommandOptionId opt_verbose = cmd.option("verbose"); CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_type = cmd.option("type"); - - /* Check the option '--file' is enabled or not + + /* Check the option '--file' is enabled or not * Actually, it must be enabled as the shell interface will check * before reaching this fuction */ @@ -520,7 +519,7 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, */ VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file)); VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty()); - + std::string file_name = cmd_context.option_value(cmd, opt_file); std::string file_type = cmd_context.option_value(cmd, opt_type); /* Write unique blocks to a file */ @@ -534,7 +533,6 @@ int write_unique_blocks_template(T& openfpga_ctx, const Command& cmd, return CMD_EXEC_FATAL_ERROR; } } - /******************************************************************** * Report reference to a file diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index eb534fcb7..66ea3deb1 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -939,7 +939,7 @@ ShellCommandId add_write_fabric_pin_physical_location_command_template( /******************************************************************** * - Add a command to Shell environment: read_unique_blocks - * - Add associated options + * - Add associated options * - Add command dependency *******************************************************************/ template @@ -1015,8 +1015,7 @@ ShellCommandId add_write_unique_blocks_command_template( return shell_cmd_id; } - - /****************************************************************** +/****************************************************************** * - Add a command to Shell environment: report_reference * - Add associated options * - Add command dependency From 172260e2fb4be78a4063561977c6829f69e447c9 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 11 Sep 2024 18:17:45 +0800 Subject: [PATCH 44/50] modified index.rst --- docs/source/manual/file_formats/index.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index 340bb3d8a..e7151f99b 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -47,3 +47,5 @@ OpenFPGA widely uses XML format for interchangeable files fabric_hierarchy_file reference_file + + unique_blocks From 27db6d24964586609c0de64a2ab95706b9478886 Mon Sep 17 00:00:00 2001 From: Lin Date: Wed, 11 Sep 2024 18:28:32 +0800 Subject: [PATCH 45/50] modified unique_block.rst --- .../manual/file_formats/unique_blocks.rst | 70 ++++++++----------- 1 file changed, 29 insertions(+), 41 deletions(-) diff --git a/docs/source/manual/file_formats/unique_blocks.rst b/docs/source/manual/file_formats/unique_blocks.rst index 0445de969..9a9e86c1d 100644 --- a/docs/source/manual/file_formats/unique_blocks.rst +++ b/docs/source/manual/file_formats/unique_blocks.rst @@ -1,62 +1,50 @@ .. _file_formats_unique_blocks: Unique Blocks (.xml) -~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~ -A unique blocks file is formatted in XML. The unique blocks can be of type ``cbx``, ``cby`` or ``sb``. As illustrated by the XML code below, the file includes the type and coordinates of these unique blocks, as well as the coordinates of their corresponding instances. +A unique blocks file is formatted in XML. The unique blocks can be of type ``cbx``, ``cby``, or ``sb``. As illustrated by the XML code below, the file includes the type and coordinates of these unique blocks, as well as the coordinates of their corresponding instances. Configurable Block -^^^^^^^^^^^^^^^^^^^ +~~~~~~~~~~~~~~~~~~ -Unique blocks can be applied to various blocks, each of which can be of type ``cbx``, ``cby`` or ``sb``, and may have different coordinates. +Unique blocks can be applied to various blocks, each of which can be of type ``cbx``, ``cby``, or ``sb``, and may have different coordinates. -.. option:: +.. note:: - For each block, a set of keys can be defined. For unique blocks, both keys and instances can be specified. However, if a unique block does not have an instance, only keys are permitted. - - - ``type`` specifies the type of the unique block in the FPGA fabric. Valid values for ``type`` are ``cbx``, ``cby`` or ``sb``. + For each block, a set of keys can be defined. For unique blocks, both keys and instances can be specified. However, if a unique block does not have an instance, only keys are permitted. - - ``x`` represents the x-coordinate of the unique block. - - - ``y`` represents the y-coordinate of the unique block. + - ``type`` specifies the type of the unique block in the FPGA fabric. Valid values for ``type`` are ``cbx``, ``cby``, or ``sb``. + - ``x`` represents the x-coordinate of the unique block. + - ``y`` represents the y-coordinate of the unique block. Configurable Instance -^^^^^^^^^^^^^^^^^^^ +~~~~~~~~~~~~~~~~~~~~~ A specific unique block can have multiple instances, where each instance is a mirrored version of the unique block. Each instance shares the same type as its parent block and includes information about its coordinates. -.. option:: - - - ``x`` specifies the x-coordinate of the instance. - - - ``y`` specifies the y-coordinate of the instance. +.. note:: + - ``x`` specifies the x-coordinate of the instance. + - ``y`` specifies the y-coordinate of the instance. The following content provides an example of a unique block file: .. code-block:: xml - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + From 5ccad723c4668a0fbabecf3e42c13dda4315675a Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 12 Sep 2024 11:16:31 +0800 Subject: [PATCH 46/50] add comments --- openfpga/src/annotation/device_rr_gsb.cpp | 19 +++++++- openfpga/src/annotation/device_rr_gsb.h | 43 +++++++++++++------ .../src/annotation/read_xml_unique_blocks.cpp | 24 ++++------- .../src/annotation/read_xml_unique_blocks.h | 14 ++---- .../annotation/write_xml_unique_blocks.cpp | 20 ++++----- .../src/annotation/write_xml_unique_blocks.h | 23 ++++------ .../base/openfpga_setup_command_template.h | 2 + 7 files changed, 80 insertions(+), 65 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index ced7e6b9d..176b0dbd3 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -65,8 +65,9 @@ size_t DeviceRRGSB::get_num_cb_unique_module(const t_rr_type& cb_type) const { exit(1); } } - +/* Identify if unique blocks are preloaded or built */ bool DeviceRRGSB::is_compressed() const { return is_compressed_; } + /* Identify if a GSB actually exists at a location */ bool DeviceRRGSB::is_gsb_exist(const RRGraphView& rr_graph, const vtr::Point coord) const { @@ -96,10 +97,12 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const { return sb_unique_module_.size(); } +/* get the coordinate of unique mirrors of switch blocks */ vtr::Point DeviceRRGSB::get_sb_unique_block_coord(size_t id) const { return sb_unique_module_[id]; } +/* get the coordinates of the instances of a unique switch block */ std::vector> DeviceRRGSB::get_sb_unique_block_instance_coord( const vtr::Point& unique_block_coord) const { auto unique_module_id = @@ -120,10 +123,12 @@ std::vector> DeviceRRGSB::get_sb_unique_block_instance_coord( return instance_map; } +/* get the coordinate of unique mirrors of connection blocks of CHANX type */ vtr::Point DeviceRRGSB::get_cbx_unique_block_coord(size_t id) const { return cbx_unique_module_[id]; } +/* get the coordinates of the instances of a unique connection block of CHANX type */ std::vector> DeviceRRGSB::get_cbx_unique_block_instance_coord( const vtr::Point& unique_block_coord) const { @@ -145,10 +150,12 @@ DeviceRRGSB::get_cbx_unique_block_instance_coord( return instance_map; } +/* get the coordinate of unique mirrors of connection blocks of CHANY type */ vtr::Point DeviceRRGSB::get_cby_unique_block_coord(size_t id) const { return cby_unique_module_[id]; } +/* get the coordinates of the instances of a unique connection block of CHANY type */ std::vector> DeviceRRGSB::get_cby_unique_block_instance_coord( const vtr::Point& unique_block_coord) const { @@ -246,6 +253,7 @@ void DeviceRRGSB::reserve(const vtr::Point& coordinate) { cby_unique_module_id_[x].resize(coordinate.y()); } } + void DeviceRRGSB::reserve_unique_modules() { /* As rr_gsb_ has been built, it has valid size. Will reserve space for * unique blocks according to rr_gsb_'s size*/ @@ -658,6 +666,11 @@ size_t DeviceRRGSB::get_cb_unique_module_index( return cb_unique_module_id; } +/************************************************************************ + * Preload unique blocks + ***********************************************************************/ +/* preload unique cbx blocks and their corresponding instance information. This + * function will be called when read_unique_blocks command invoked */ void DeviceRRGSB::preload_unique_cbx_module( const vtr::Point& block_coordinate, const std::vector>& instance_coords) { @@ -682,6 +695,8 @@ void DeviceRRGSB::preload_unique_cbx_module( } } +/* preload unique cby blocks and their corresponding instance information. This + * function will be called when read_unique_blocks command invoked */ void DeviceRRGSB::preload_unique_cby_module( const vtr::Point& block_coordinate, const std::vector>& instance_coords) { @@ -707,6 +722,8 @@ void DeviceRRGSB::preload_unique_cby_module( } } +/* preload unique sb blocks and their corresponding instance information. This + * function will be called when read_unique_blocks command invoked */ void DeviceRRGSB::preload_unique_sb_module( const vtr::Point& block_coordinate, const std::vector>& instance_coords) { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index e40a81892..2155ef21a 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -44,17 +44,24 @@ class DeviceRRGSB { size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ - size_t get_num_sb_unique_module() const; - vtr::Point get_sb_unique_block_coord(size_t id) const; + size_t get_num_sb_unique_module() + const; /* get the number of unique mirrors of SB */ + vtr::Point get_sb_unique_block_coord( + size_t id) const; /* get the coordinate of a unique switch block */ std::vector> get_sb_unique_block_instance_coord( - const vtr::Point& unique_block_coord) const; + const vtr::Point& unique_block_coord) + const; /* get the coordinates of the instances of a unique switch block */ - vtr::Point get_cbx_unique_block_coord(size_t id) const; + vtr::Point get_cbx_unique_block_coord( + size_t id) const; /* get the coordinate of a unique connection block of CHANX type */ std::vector> get_cbx_unique_block_instance_coord( - const vtr::Point& unique_block_coord) const; - vtr::Point get_cby_unique_block_coord(size_t id) const; + const vtr::Point& unique_block_coord) + const; /* get the coordinates of the instances of a unique connection block of CHANX type*/ + vtr::Point get_cby_unique_block_coord( + size_t id) const; /* get the coordinate of a unique connection block of CHANY type */ std::vector> get_cby_unique_block_instance_coord( - const vtr::Point& unique_block_coord) const; + const vtr::Point& unique_block_coord) + const; /* get the coordinates of the instances of a unique connection block of CHANY type */ const RRGSB& get_gsb_unique_module( const size_t& index) const; /* Get a rr-gsb which is a unique mirror */ @@ -110,14 +117,22 @@ class DeviceRRGSB { void clear(); /* clean the content */ void preload_unique_cbx_module( const vtr::Point& block_coordinate, - const std::vector>& instance_coords); + const std::vector>& + instance_coords); /* preload unique CBX blocks and their corresponding + instance information. This function will be called + when read_unique_blocks command invoked */ void preload_unique_cby_module( const vtr::Point& block_coordinate, - const std::vector>& instance_coords); - void preload_unique_sb_module( - const vtr::Point& block_coordinate, - const std::vector>& instance_coords); - void clear_unique_modules(); + const std::vector>& + instance_coords); /* preload unique CBY blocks and their corresponding +instance information. This function will be called +when read_unique_blocks command invoked */ + void preload_unique_sb_module(const vtr::Point& block_coordinate, + const std::vector>& + instance_coords); /* preload unique SB blocks + and their corresponding instance information. This function + will be called when read_unique_blocks command invoked */ + void clear_unique_modules();/* clean the content of unique blocks*/ private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ @@ -160,7 +175,7 @@ class DeviceRRGSB { private: /* Internal Data */ std::vector> rr_gsb_; - bool is_compressed_ = false; // is_valid + bool is_compressed_ = false; /* True if the unique blocks have been preloaded or built */ std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/annotation/read_xml_unique_blocks.cpp b/openfpga/src/annotation/read_xml_unique_blocks.cpp index 8abcaf3cd..6b3810602 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/read_xml_unique_blocks.cpp @@ -1,14 +1,4 @@ - -/******************************************************************** - * This file includes the top-level functions of this library - * which includes: - * -- reads an XML file of unique blocks to the associated - * data structures: device_rr_gsb - * -- write device__rr_gsb's info about unique blocks to a xml file - *******************************************************************/ - #include - /* Headers from pugi XML library */ #include "pugixml.hpp" #include "pugixml_util.hpp" @@ -29,11 +19,13 @@ #include "write_xml_utils.h" /******************************************************************** - * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror of unique module. + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb *******************************************************************/ namespace openfpga { - +/*read the instances' coordinate of a unique block from a xml file*/ std::vector> read_xml_unique_instance_coords( const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) { std::vector> instance_coords; @@ -48,6 +40,7 @@ std::vector> read_xml_unique_instance_coords( return instance_coords; } +/*read the unique block coordinate from a xml file */ vtr::Point read_xml_unique_block_coord( const pugi::xml_node& xml_block_info, const pugiutil::loc_data& loc_data) { int block_x = get_attribute(xml_block_info, "x", loc_data).as_int(); @@ -56,6 +49,7 @@ vtr::Point read_xml_unique_block_coord( return block_coordinate; } +/*report information of read unique blocks*/ void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, bool verbose_output) { /* Report the stats */ @@ -102,9 +96,7 @@ void report_unique_module_status_read(const DeviceRRGSB& device_rr_gsb, 1.)); } -/******************************************************************** - * Parse XML codes about to an object of device_rr_gsb - *******************************************************************/ +/*Parse XML codes about to an object of device_rr_gsb*/ int read_xml_unique_blocks(DeviceRRGSB& device_rr_gsb, const char* file_name, bool verbose_output) { vtr::ScopedStartFinishTimer timer("Read unique blocks xml file"); diff --git a/openfpga/src/annotation/read_xml_unique_blocks.h b/openfpga/src/annotation/read_xml_unique_blocks.h index b1885fca7..3e5e22c62 100644 --- a/openfpga/src/annotation/read_xml_unique_blocks.h +++ b/openfpga/src/annotation/read_xml_unique_blocks.h @@ -1,14 +1,6 @@ #ifndef READ_XML_UNIQUE_BLOCKS_H #define READ_XML_UNIQUE_BLOCKS_H -/******************************************************************** - * This file includes the top-level functions of this library - * which includes: - * -- reads an XML file of unique blocks to the associated - * data structures: device_rr_gsb - * -- write device__rr_gsb's info about unique blocks to a xml file - *******************************************************************/ - #include /* Headers from pugi XML library */ @@ -25,8 +17,10 @@ #include "device_rr_gsb_utils.h" /******************************************************************** - * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror of unique module. + * This file includes the top-level functions of this library + * which includes: + * -- reads an XML file of unique blocks to the associated + * data structures: device_rr_gsb *******************************************************************/ namespace openfpga { diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index 3550af531..37b8a7483 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -1,12 +1,4 @@ -/******************************************************************** - * This file includes the top-level functions of this library - * which includes: - * -- reads an XML file of unique blocks to the associated - * data structures: device_rr_gsb - * -- write device__rr_gsb's info about unique blocks to a xml file - *******************************************************************/ - #include /* Headers from pugi XML library */ @@ -27,11 +19,17 @@ #include "rr_gsb.h" #include "write_xml_unique_blocks.h" #include "write_xml_utils.h" + /******************************************************************** - * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror of unique module. + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a XML file *******************************************************************/ namespace openfpga { + +/*Write unique blocks and their corresponding instances' information from + *device_rr_gsb to a XML file*/ int write_xml_atom_block(std::fstream& fp, const std::vector>& instance_map, const vtr::Point& unique_block_coord, @@ -69,6 +67,7 @@ int write_xml_atom_block(std::fstream& fp, return openfpga::CMD_EXEC_SUCCESS; } +/* Report information about written unique blocks */ void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, bool verbose_output) { /* Report the stats */ @@ -116,6 +115,7 @@ void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, 1.)); } +/*Top level function to write the xml file of unique blocks*/ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output) { vtr::ScopedStartFinishTimer timer("Write unique blocks..."); diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h index 7eb8422ae..cd601763b 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.h +++ b/openfpga/src/annotation/write_xml_unique_blocks.h @@ -1,14 +1,6 @@ #ifndef WRITE_XML_UNIQUE_BLOCKS_H #define WRITE_XML_UNIQUE_BLOCKS_H -/******************************************************************** - * This file includes the top-level functions of this library - * which includes: - * -- reads an XML file of unique blocks to the associated - * data structures: device_rr_gsb - * -- write device__rr_gsb's info about unique blocks to a xml file - *******************************************************************/ - #include /* Headers from pugi XML library */ @@ -24,18 +16,21 @@ #include "arch_error.h" #include "device_rr_gsb_utils.h" -/******************************************************************** - * Parse XML codes of a to an object of device_rr_gsb - * instance is the mirror of unique module. - *******************************************************************/ -namespace openfpga { +/******************************************************************** + * This file includes the top-level functions of this library + * which includes: + * -- write the unique blocks' information in the associated data structures: + *device_rr_gsb to a XML file + *******************************************************************/ + +namespace openfpga { int write_xml_atom_block(std::fstream& fp, const std::vector>& instance_map, const vtr::Point& unique_block_coord, std::string type); void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, - bool verbose_output); + bool verbose_output); /*report status of written info*/ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); } // namespace openfpga diff --git a/openfpga/src/base/openfpga_setup_command_template.h b/openfpga/src/base/openfpga_setup_command_template.h index 66ea3deb1..3c8c41f77 100644 --- a/openfpga/src/base/openfpga_setup_command_template.h +++ b/openfpga/src/base/openfpga_setup_command_template.h @@ -1323,6 +1323,8 @@ void add_setup_command_templates(openfpga::Shell& shell, /******************************** * Command 'read_unique_blocks' */ + /* The command should NOT be executed before + * 'link_openfpga_arch' */ std::vector cmd_dependency_read_unique_blocks_command; cmd_dependency_read_unique_blocks_command.push_back(link_arch_cmd_id); add_read_unique_blocks_command_template( From 41d38193d3575817e5c05cc99a7ac1d6f756063b Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 12 Sep 2024 11:18:25 +0800 Subject: [PATCH 47/50] reformat code --- openfpga/src/annotation/device_rr_gsb.cpp | 6 ++++-- openfpga/src/annotation/device_rr_gsb.h | 19 +++++++++++-------- .../annotation/write_xml_unique_blocks.cpp | 4 ++-- .../src/annotation/write_xml_unique_blocks.h | 8 ++++---- 4 files changed, 21 insertions(+), 16 deletions(-) diff --git a/openfpga/src/annotation/device_rr_gsb.cpp b/openfpga/src/annotation/device_rr_gsb.cpp index 176b0dbd3..2886b378a 100644 --- a/openfpga/src/annotation/device_rr_gsb.cpp +++ b/openfpga/src/annotation/device_rr_gsb.cpp @@ -128,7 +128,8 @@ vtr::Point DeviceRRGSB::get_cbx_unique_block_coord(size_t id) const { return cbx_unique_module_[id]; } -/* get the coordinates of the instances of a unique connection block of CHANX type */ +/* get the coordinates of the instances of a unique connection block of CHANX + * type */ std::vector> DeviceRRGSB::get_cbx_unique_block_instance_coord( const vtr::Point& unique_block_coord) const { @@ -155,7 +156,8 @@ vtr::Point DeviceRRGSB::get_cby_unique_block_coord(size_t id) const { return cby_unique_module_[id]; } -/* get the coordinates of the instances of a unique connection block of CHANY type */ +/* get the coordinates of the instances of a unique connection block of CHANY + * type */ std::vector> DeviceRRGSB::get_cby_unique_block_instance_coord( const vtr::Point& unique_block_coord) const { diff --git a/openfpga/src/annotation/device_rr_gsb.h b/openfpga/src/annotation/device_rr_gsb.h index 2155ef21a..1325b557b 100644 --- a/openfpga/src/annotation/device_rr_gsb.h +++ b/openfpga/src/annotation/device_rr_gsb.h @@ -52,16 +52,18 @@ class DeviceRRGSB { const vtr::Point& unique_block_coord) const; /* get the coordinates of the instances of a unique switch block */ - vtr::Point get_cbx_unique_block_coord( - size_t id) const; /* get the coordinate of a unique connection block of CHANX type */ + vtr::Point get_cbx_unique_block_coord(size_t id) + const; /* get the coordinate of a unique connection block of CHANX type */ std::vector> get_cbx_unique_block_instance_coord( const vtr::Point& unique_block_coord) - const; /* get the coordinates of the instances of a unique connection block of CHANX type*/ - vtr::Point get_cby_unique_block_coord( - size_t id) const; /* get the coordinate of a unique connection block of CHANY type */ + const; /* get the coordinates of the instances of a unique connection block + of CHANX type*/ + vtr::Point get_cby_unique_block_coord(size_t id) + const; /* get the coordinate of a unique connection block of CHANY type */ std::vector> get_cby_unique_block_instance_coord( const vtr::Point& unique_block_coord) - const; /* get the coordinates of the instances of a unique connection block of CHANY type */ + const; /* get the coordinates of the instances of a unique connection block + of CHANY type */ const RRGSB& get_gsb_unique_module( const size_t& index) const; /* Get a rr-gsb which is a unique mirror */ @@ -132,7 +134,7 @@ when read_unique_blocks command invoked */ instance_coords); /* preload unique SB blocks and their corresponding instance information. This function will be called when read_unique_blocks command invoked */ - void clear_unique_modules();/* clean the content of unique blocks*/ + void clear_unique_modules(); /* clean the content of unique blocks*/ private: /* Internal cleaners */ void clear_gsb(); /* clean the content */ @@ -175,7 +177,8 @@ when read_unique_blocks command invoked */ private: /* Internal Data */ std::vector> rr_gsb_; - bool is_compressed_ = false; /* True if the unique blocks have been preloaded or built */ + bool is_compressed_ = + false; /* True if the unique blocks have been preloaded or built */ std::vector> gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ diff --git a/openfpga/src/annotation/write_xml_unique_blocks.cpp b/openfpga/src/annotation/write_xml_unique_blocks.cpp index 37b8a7483..c7f0351d4 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.cpp +++ b/openfpga/src/annotation/write_xml_unique_blocks.cpp @@ -24,10 +24,10 @@ * This file includes the top-level functions of this library * which includes: * -- write the unique blocks' information in the associated data structures: - *device_rr_gsb to a XML file + *device_rr_gsb to a XML file *******************************************************************/ namespace openfpga { - + /*Write unique blocks and their corresponding instances' information from *device_rr_gsb to a XML file*/ int write_xml_atom_block(std::fstream& fp, diff --git a/openfpga/src/annotation/write_xml_unique_blocks.h b/openfpga/src/annotation/write_xml_unique_blocks.h index cd601763b..2fde43845 100644 --- a/openfpga/src/annotation/write_xml_unique_blocks.h +++ b/openfpga/src/annotation/write_xml_unique_blocks.h @@ -16,12 +16,11 @@ #include "arch_error.h" #include "device_rr_gsb_utils.h" - /******************************************************************** * This file includes the top-level functions of this library * which includes: * -- write the unique blocks' information in the associated data structures: - *device_rr_gsb to a XML file + *device_rr_gsb to a XML file *******************************************************************/ namespace openfpga { @@ -29,8 +28,9 @@ int write_xml_atom_block(std::fstream& fp, const std::vector>& instance_map, const vtr::Point& unique_block_coord, std::string type); -void report_unique_module_status_write(const DeviceRRGSB& device_rr_gsb, - bool verbose_output); /*report status of written info*/ +void report_unique_module_status_write( + const DeviceRRGSB& device_rr_gsb, + bool verbose_output); /*report status of written info*/ int write_xml_unique_blocks(const DeviceRRGSB& device_rr_gsb, const char* fname, bool verbose_output); } // namespace openfpga From e6c43ec9ad3f28b11ed7cc5eb1068fcf3362cb5c Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 12 Sep 2024 11:41:52 +0800 Subject: [PATCH 48/50] add command doc --- .../openfpga_commands/setup_commands.rst | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index b2e10d1b6..d2a7635e3 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -545,6 +545,44 @@ report_reference Do not print time stamp in output files + .. option:: --verbose + + Show verbose info + +.. _openfpga_setup_commands_read_unique_blocks: + +read_unique_blocks +~~~~~~~~~~~~~~~~~~~~ + + Read information of unique blocks from a given file + + .. option:: --file or -f + + Specify the file which contains unique block information + + .. option:: --type + + Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML + + .. option:: --verbose + + Show verbose info + +.. _openfpga_setup_commands_write_unique_blocks: + +write_unique_blocks +~~~~~~~~~~~~~~~~~~~~~ + + Write information of unique blocks from internal data structure to a given file + + .. option:: --file or -f + + Specify the file which we will write unique block information to + + .. option:: --type + + Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML + .. option:: --verbose Show verbose info \ No newline at end of file From 52f5cf03996a800f40fd2f2836617f97c7b776c5 Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 12 Sep 2024 13:36:06 +0800 Subject: [PATCH 49/50] add link to command doc --- .../openfpga_shell/openfpga_commands/setup_commands.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index d2a7635e3..3738c78b0 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -556,9 +556,9 @@ read_unique_blocks Read information of unique blocks from a given file - .. option:: --file or -f + .. option:: --file - Specify the file which contains unique block information + Specify the file which contains unique block information. See details in :ref:`_file_formats_unique_blocks` .. option:: --type @@ -575,9 +575,9 @@ write_unique_blocks Write information of unique blocks from internal data structure to a given file - .. option:: --file or -f + .. option:: --file - Specify the file which we will write unique block information to + Specify the file which we will write unique block information to. See details in :ref:`_file_formats_unique_blocks` .. option:: --type From 423e15289c94569649569c0a3847128882b21f18 Mon Sep 17 00:00:00 2001 From: Lin Date: Thu, 12 Sep 2024 13:47:10 +0800 Subject: [PATCH 50/50] add link to command doc, valid now --- docs/source/manual/file_formats/unique_blocks.rst | 2 +- .../openfpga_commands/setup_commands.rst | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/source/manual/file_formats/unique_blocks.rst b/docs/source/manual/file_formats/unique_blocks.rst index 9a9e86c1d..ace724cc4 100644 --- a/docs/source/manual/file_formats/unique_blocks.rst +++ b/docs/source/manual/file_formats/unique_blocks.rst @@ -1,7 +1,7 @@ .. _file_formats_unique_blocks: Unique Blocks (.xml) -~~~~~~~~~~~~~~~~~~~~ +-------------------- A unique blocks file is formatted in XML. The unique blocks can be of type ``cbx``, ``cby``, or ``sb``. As illustrated by the XML code below, the file includes the type and coordinates of these unique blocks, as well as the coordinates of their corresponding instances. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index 3738c78b0..103e245ab 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -554,15 +554,15 @@ report_reference read_unique_blocks ~~~~~~~~~~~~~~~~~~~~ - Read information of unique blocks from a given file + Read information of unique blocks from a given file. .. option:: --file - Specify the file which contains unique block information. See details in :ref:`_file_formats_unique_blocks` + Specify the file which contains unique block information. See details in :ref:`file_formats_unique_blocks`. .. option:: --type - Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML + Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML. .. option:: --verbose @@ -573,15 +573,15 @@ read_unique_blocks write_unique_blocks ~~~~~~~~~~~~~~~~~~~~~ - Write information of unique blocks from internal data structure to a given file + Write information of unique blocks from internal data structure to a given file. .. option:: --file - Specify the file which we will write unique block information to. See details in :ref:`_file_formats_unique_blocks` + Specify the file which we will write unique block information to. See details in :ref:`file_formats_unique_blocks`. .. option:: --type - Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML + Specify the type of the unique blocks file [xml|bin]. If not specified, by default it is XML. .. option:: --verbose