[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr

openfpga_flow/scripts/run_fpga_task.py

@@ -279,7 +279,6 @@ def generate_each_task_actions(taskname):
                                   "for vpr_blif flow")
             CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act")
 
-        # Allow user to specify a post-synthesis verilog file for simulation usage
             # Check if base verilog file exists
             if not SynthSection.get(bech_name+"_verilog"):
                 clean_up_and_exit("Missing argument %s for vpr_blif flow" %