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add XML writer for design technology of a circuit model

This commit is contained in:
tangxifan 2020-01-16 14:45:41 -07:00
parent 3ace7f8ef7
commit 0304d723c0
7 changed files with 275 additions and 53 deletions
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84
libopenfpga/libarchopenfpga/arch/sample_arch.xml
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@ -8,43 +8,18 @@
each primitives in FPGA architecture
-->
<openfpga_architecture>
<simulation_parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimuli>
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimuli>
</simulation_parameters>
<tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
<technology>
<library lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
<transistors pn_ratio="2" model_ref="M">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</transistors>
</technology>
<circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
<design_technology type="cmos" topology="inverter" size="1" tapered="false"/>
<design_technology type="cmos" topology="inverter" size="1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -55,7 +30,7 @@
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" tapered="true" tap_drive_level="2" f_per_stage="4"/>
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -66,7 +41,7 @@
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
<design_technology type="cmos" topology="buffer" size="1" tapered="true" tap_drive_level="3" f_per_stage="4"/>
<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
@ -122,7 +97,7 @@
<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<!--mux2to1 subckt_name="mux2to1"/-->
@ -132,7 +107,7 @@
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="multi-level" num_level="2" add_const_input="true" const_input_val="1"/>
<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
@ -142,7 +117,7 @@
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/>
<!--mux2to1 subckt_name="mux2to1"/-->
@ -258,3 +233,32 @@
</circuit_model>
</circuit_library>
</openfpga_architecture>
<openfpga_verification>
<simulation_parameters>
<options sim_temp="25" post="off" captab="off" fast="on"/>
<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
</slew>
<delay>
<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
</delay>
</measure>
<stimuli>
<clock op_freq="200e6" sim_slack="0.2" prog_freq="10e6">
<rise slew_time="20e-12" slew_type="abs"/>
<fall slew_time="20e-12" slew_type="abs"/>
</clock>
<input>
<rise slew_time="25e-12" slew_type="abs"/>
<fall slew_time="25e-12" slew_type="abs"/>
</input>
</stimuli>
</simulation_parameters>
</openfpga_verification>

103
libopenfpga/libarchopenfpga/src/circuit_library.cpp
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@ -244,6 +244,24 @@ enum e_circuit_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(c
return pass_gate_logic_types_[model_id];
}
/* Return the pmos size of a pass gate logic module, only applicable to circuit model whose type is pass-gate logic */
float CircuitLibrary::pass_gate_logic_pmos_size(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the type of this model should be PASSGATE */
VTR_ASSERT(CIRCUIT_MODEL_PASSGATE == model_type(model_id));
return pass_gate_logic_sizes_[model_id].y();
}
/* Return the nmos size of a pass gate logic module, only applicable to circuit model whose type is pass-gate logic */
float CircuitLibrary::pass_gate_logic_nmos_size(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the type of this model should be PASSGATE */
VTR_ASSERT(CIRCUIT_MODEL_PASSGATE == model_type(model_id));
return pass_gate_logic_sizes_[model_id].x();
}
/* Return the type of multiplexing structure of a circuit model */
enum e_circuit_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const {
/* validate the model_id */
@ -305,6 +323,18 @@ bool CircuitLibrary::mux_use_local_encoder(const CircuitModelId& model_id) const
return mux_use_local_encoder_[model_id];
}
/* Return if circuit model uses advanced RRAM design
* Only applicable for MUX/LUT circuit model
*/
bool CircuitLibrary::mux_use_advanced_rram_design(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate the circuit model type is MUX */
VTR_ASSERT( (CIRCUIT_MODEL_MUX == model_type(model_id))
|| (CIRCUIT_MODEL_LUT == model_type(model_id)) );
return mux_use_advanced_rram_design_[model_id];
}
/* Return the type of gate for a circuit model
* Only applicable for GATE circuit model
*/
@ -327,6 +357,17 @@ enum e_circuit_model_buffer_type CircuitLibrary::buffer_type(const CircuitModelI
return buffer_types_[model_id];
}
/* Return the size of buffer for a circuit model
* Only applicable for BUF/INV circuit model
*/
size_t CircuitLibrary::buffer_size(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate the circuit model type is MUX */
VTR_ASSERT(CIRCUIT_MODEL_INVBUF == model_type(model_id));
return buffer_sizes_[model_id];
}
/* Return the number of levels of buffer for a circuit model
* Only applicable for BUF/INV circuit model
*/
@ -338,6 +379,17 @@ size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const {
return buffer_num_levels_[model_id];
}
/* Return the driving strength per level of buffer for a circuit model
* Only applicable for BUF/INV circuit model
*/
size_t CircuitLibrary::buffer_f_per_stage(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate the circuit model type is BUF */
VTR_ASSERT(CIRCUIT_MODEL_INVBUF == model_type(model_id));
return buffer_f_per_stage_[model_id];
}
/* Find the circuit model id of the input buffer of a circuit model */
CircuitModelId CircuitLibrary::input_buffer_model(const CircuitModelId& model_id) const {
/* validate the model_id */
@ -369,6 +421,57 @@ size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const {
return delay_types_[model_id].size();
}
/* Return the Low Resistance State Resistance of a RRAM model */
float CircuitLibrary::rram_rlrs(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the design_tech of this model should be RRAM */
VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id));
return rram_res_[model_id].x();
}
/* Return the High Resistance State Resistance of a RRAM model */
float CircuitLibrary::rram_rhrs(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the design_tech of this model should be RRAM */
VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id));
return rram_res_[model_id].y();
}
/* Return the size of PMOS transistor to set a RRAM model */
float CircuitLibrary::rram_wprog_set_pmos(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the design_tech of this model should be RRAM */
VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id));
return wprog_set_[model_id].y();
}
float CircuitLibrary::rram_wprog_set_nmos(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the design_tech of this model should be RRAM */
VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id));
return wprog_set_[model_id].x();
}
float CircuitLibrary::rram_wprog_reset_pmos(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the design_tech of this model should be RRAM */
VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id));
return wprog_reset_[model_id].y();
}
float CircuitLibrary::rram_wprog_reset_nmos(const CircuitModelId& model_id) const {
/* validate the model_id */
VTR_ASSERT(valid_model_id(model_id));
/* validate that the design_tech of this model should be RRAM */
VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id));
return wprog_reset_[model_id].x();
}
/************************************************************************
* Public Accessors : Basic data query on Circuit models' Circuit Port
***********************************************************************/

12
libopenfpga/libarchopenfpga/src/circuit_library.h
View File

@ -198,21 +198,33 @@ class CircuitLibrary {
/* Pass-gate-logic information */
CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const;
enum e_circuit_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const;
float pass_gate_logic_pmos_size(const CircuitModelId& model_id) const;
float pass_gate_logic_nmos_size(const CircuitModelId& model_id) const;
/* Multiplexer information */
enum e_circuit_model_structure mux_structure(const CircuitModelId& model_id) const;
size_t mux_num_levels(const CircuitModelId& model_id) const;
bool mux_add_const_input(const CircuitModelId& model_id) const;
size_t mux_const_input_value(const CircuitModelId& model_id) const;
bool mux_use_local_encoder(const CircuitModelId& model_id) const;
bool mux_use_advanced_rram_design(const CircuitModelId& model_id) const;
/* Gate information */
enum e_circuit_model_gate_type gate_type(const CircuitModelId& model_id) const;
/* Buffer information */
enum e_circuit_model_buffer_type buffer_type(const CircuitModelId& model_id) const;
size_t buffer_size(const CircuitModelId& model_id) const;
size_t buffer_num_levels(const CircuitModelId& model_id) const;
size_t buffer_f_per_stage(const CircuitModelId& model_id) const;
CircuitModelId input_buffer_model(const CircuitModelId& model_id) const;
CircuitModelId output_buffer_model(const CircuitModelId& model_id) const;
/* Delay information */
size_t num_delay_info(const CircuitModelId& model_id) const;
/* RRAM information */
float rram_rlrs(const CircuitModelId& model_id) const;
float rram_rhrs(const CircuitModelId& model_id) const;
float rram_wprog_set_pmos(const CircuitModelId& model_id) const;
float rram_wprog_set_nmos(const CircuitModelId& model_id) const;
float rram_wprog_reset_pmos(const CircuitModelId& model_id) const;
float rram_wprog_reset_nmos(const CircuitModelId& model_id) const;
public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/
CircuitPortId model_port(const CircuitModelId& model_id, const std::string& name) const;
size_t num_model_ports(const CircuitModelId& model_id) const;

26
libopenfpga/libarchopenfpga/src/circuit_types.h
View File

@ -16,12 +16,6 @@
/* Header files should be included in a sequence */
/* Standard header files required go first */
enum e_circuit_model_delay_type {
CIRCUIT_MODEL_DELAY_RISE,
CIRCUIT_MODEL_DELAY_FALL,
NUM_CIRCUIT_MODEL_DELAY_TYPES
};
/*Struct for a CIRCUIT model of a module*/
enum e_circuit_model_type {
CIRCUIT_MODEL_CHAN_WIRE,
@ -46,6 +40,8 @@ enum e_circuit_model_design_tech {
CIRCUIT_MODEL_DESIGN_RRAM,
NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES
};
/* Strings correspond to each design technology type */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES> CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING = {{"cmos", "rram"}};
enum e_circuit_model_structure {
CIRCUIT_MODEL_STRUCTURE_TREE,
@ -55,13 +51,15 @@ enum e_circuit_model_structure {
NUM_CIRCUIT_MODEL_STRUCTURE_TYPES
};
/* Strings correspond to each type of mux structure */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_STRUCTURE_TYPES> CIRCUIT_MODEL_STRUCTURE_TYPE_STRING = {{"TREE-LIKE", "ONE-LEVEL", "MULTI-LEVEL", "CROSSBAR"}};
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_STRUCTURE_TYPES> CIRCUIT_MODEL_STRUCTURE_TYPE_STRING = {{"tree", "one_level", "multi_level", "crossbar"}};
enum e_circuit_model_buffer_type {
CIRCUIT_MODEL_BUF_INV,
CIRCUIT_MODEL_BUF_BUF,
NUM_CIRCUIT_MODEL_BUF_TYPES
};
/* Strings correspond to each type of buffer */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_BUF_TYPES> CIRCUIT_MODEL_BUFFER_TYPE_STRING = {{"inverter", "buffer"}};
enum e_circuit_model_pass_gate_logic_type {
CIRCUIT_MODEL_PASS_GATE_TRANSMISSION,
@ -70,6 +68,8 @@ enum e_circuit_model_pass_gate_logic_type {
CIRCUIT_MODEL_PASS_GATE_STDCELL, /* Standard cell as a special type of pass-gate logic */
NUM_CIRCUIT_MODEL_PASS_GATE_TYPES
};
/* Strings correspond to each type of buffer */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_PASS_GATE_TYPES> CIRCUIT_MODEL_PASSGATE_TYPE_STRING = {{"transmission_gate", "pass_transistor", "rram", "standard_cell"}};
enum e_circuit_model_gate_type {
CIRCUIT_MODEL_GATE_AND,
@ -77,6 +77,8 @@ enum e_circuit_model_gate_type {
CIRCUIT_MODEL_GATE_MUX2,
NUM_CIRCUIT_MODEL_GATE_TYPES
};
/* Strings correspond to each type of logic gate */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_GATE_TYPES> CIRCUIT_MODEL_GATE_TYPE_STRING = {{"AND", "OR", "MUX2"}};
enum e_wire_model_type {
WIRE_MODEL_PI,
@ -97,7 +99,13 @@ enum e_circuit_model_port_type {
NUM_CIRCUIT_MODEL_PORT_TYPES
};
/* Strings correspond to each port type */
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_PORT_TYPES> CIRCUIT_MODEL_PORT_TYPE_STRING = {{"INPUT", "OUTPUT", "INOUT", "CLOCK", "SRAM", "BL", "BLB", "WL", "WLB"}};
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_PORT_TYPES> CIRCUIT_MODEL_PORT_TYPE_STRING = {{"input", "output", "inout", "clock", "sram", "bl", "blb", "wl", "wlb"}};
enum e_circuit_model_delay_type {
CIRCUIT_MODEL_DELAY_RISE,
CIRCUIT_MODEL_DELAY_FALL,
NUM_CIRCUIT_MODEL_DELAY_TYPES
};
/* For SRAM */
enum e_sram_orgz {
@ -108,6 +116,6 @@ enum e_sram_orgz {
NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES
};
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES> CIRCUIT_MODEL_SRAM_ORGZ_TYPE_STRING = {{"STANDALONE", "SCAN-CHAIN", "MEMORY_BANK", "LOCAL_ENCODER"}};
constexpr std::array<const char*, NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES> CIRCUIT_MODEL_SRAM_ORGZ_TYPE_STRING = {{"standalone", "scan_chain", "memory_bank", "local_encoder"}};
#endif

13
libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
View File

@ -135,11 +135,11 @@ e_circuit_model_structure string_to_mux_structure_type(const std::string& type_s
return CIRCUIT_MODEL_STRUCTURE_TREE;
}
if (std::string("one-level") == type_string) {
if (std::string("one_level") == type_string) {
return CIRCUIT_MODEL_STRUCTURE_ONELEVEL;
}
if (std::string("multi-level") == type_string) {
if (std::string("multi_level") == type_string) {
return CIRCUIT_MODEL_STRUCTURE_MULTILEVEL;
}
@ -289,7 +289,7 @@ void read_xml_model_design_technology(pugi::xml_node& xml_model,
* 3. driving strength per stage
*/
circuit_lib.set_buffer_size(model, get_attribute(xml_design_tech, "size", loc_data).as_float(0.));
circuit_lib.set_buffer_num_levels(model, get_attribute(xml_design_tech, "tap_drive_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
circuit_lib.set_buffer_num_levels(model, get_attribute(xml_design_tech, "num_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(1));
circuit_lib.set_buffer_f_per_stage(model, get_attribute(xml_design_tech, "f_per_stage", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(4));
}
@ -358,6 +358,13 @@ void read_xml_model_design_technology(pugi::xml_node& xml_model,
}
if (CIRCUIT_MODEL_STRUCTURE_MULTILEVEL == circuit_lib.mux_structure(model)) {
circuit_lib.set_mux_num_levels(model, get_attribute(xml_design_tech, "num_level", loc_data).as_int(1));
/* Correction on the mux structure:
* if the number of level is set to 1 in a multi-level multiplexer,
* we change the mux structure to one-level
*/
if (1 == circuit_lib.mux_num_levels(model)) {
circuit_lib.set_mux_structure(model, CIRCUIT_MODEL_STRUCTURE_ONELEVEL);
}
}
circuit_lib.set_mux_use_advanced_rram_design(model, get_attribute(xml_design_tech, "advanced_rram_design", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
circuit_lib.set_mux_use_local_encoder(model, get_attribute(xml_design_tech, "local_encoder", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));

89
libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
View File

@ -12,6 +12,86 @@
#include "write_xml_utils.h"
#include "write_xml_circuit_library.h"
/********************************************************************
* A writer to output the design technology of a circuit model to XML format
*******************************************************************/
static
void write_xml_design_technology(std::fstream& fp,
const char* fname,
const CircuitLibrary& circuit_lib,
const CircuitModelId& model) {
/* Validate the file stream */
openfpga::check_file_stream(fname, fp);
fp << "\t\t\t" << "<design_technology";
write_xml_attribute(fp, "type", CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING[circuit_lib.design_tech_type(model)]);
if (true == circuit_lib.is_power_gated(model)) {
write_xml_attribute(fp, "power_gated", "true");
}
/* Buffer-related information */
if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model)) {
write_xml_attribute(fp, "topology", CIRCUIT_MODEL_BUFFER_TYPE_STRING[circuit_lib.buffer_type(model)]);
write_xml_attribute(fp, "size", std::to_string(circuit_lib.buffer_size(model)).c_str());
if (1 < circuit_lib.buffer_num_levels(model)) {
write_xml_attribute(fp, "num_level", std::to_string(circuit_lib.buffer_num_levels(model)).c_str());
write_xml_attribute(fp, "f_per_stage", std::to_string(circuit_lib.buffer_f_per_stage(model)).c_str());
}
}
/* Pass-gate-logic -related information */
if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(model)) {
write_xml_attribute(fp, "topology", CIRCUIT_MODEL_PASSGATE_TYPE_STRING[circuit_lib.pass_gate_logic_type(model)]);
write_xml_attribute(fp, "pmos_size", std::to_string(circuit_lib.pass_gate_logic_pmos_size(model)).c_str());
write_xml_attribute(fp, "nmos_size", std::to_string(circuit_lib.pass_gate_logic_nmos_size(model)).c_str());
}
/* Look-Up Table (LUT)-related information */
if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
if (true == circuit_lib.is_lut_fracturable(model)) {
write_xml_attribute(fp, "fracturable_lut", "true");
}
}
/* Multiplexer-related information */
if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
write_xml_attribute(fp, "structure", CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[circuit_lib.mux_structure(model)]);
if (true == circuit_lib.mux_add_const_input(model)) {
write_xml_attribute(fp, "add_const_input", "true");
write_xml_attribute(fp, "const_input_val", std::to_string(circuit_lib.mux_const_input_value(model)).c_str());
}
if (CIRCUIT_MODEL_STRUCTURE_MULTILEVEL == circuit_lib.mux_structure(model)) {
write_xml_attribute(fp, "num_level", std::to_string(circuit_lib.mux_num_levels(model)).c_str());
}
if (true == circuit_lib.mux_use_advanced_rram_design(model)) {
write_xml_attribute(fp, "advanced_rram_design", "true");
}
if (true == circuit_lib.mux_use_local_encoder(model)) {
write_xml_attribute(fp, "local_encoder", "true");
}
}
/* Gate-related information */
if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(model)) {
write_xml_attribute(fp, "topology", CIRCUIT_MODEL_GATE_TYPE_STRING[circuit_lib.gate_type(model)]);
}
/* ReRAM-related information */
if (CIRCUIT_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(model)) {
write_xml_attribute(fp, "ron", std::to_string(circuit_lib.rram_rlrs(model)).c_str());
write_xml_attribute(fp, "roff", std::to_string(circuit_lib.rram_rhrs(model)).c_str());
write_xml_attribute(fp, "wprog_set_pmos", std::to_string(circuit_lib.rram_wprog_set_pmos(model)).c_str());
write_xml_attribute(fp, "wprog_set_nmos", std::to_string(circuit_lib.rram_wprog_set_nmos(model)).c_str());
write_xml_attribute(fp, "wprog_reset_pmos", std::to_string(circuit_lib.rram_wprog_reset_pmos(model)).c_str());
write_xml_attribute(fp, "wprog_reset_nmos", std::to_string(circuit_lib.rram_wprog_reset_nmos(model)).c_str());
}
/* Finish all the attributes, we can return here */
fp << "/>" << "\n";
return;
}
/********************************************************************
* A writer to output a circuit model to XML format
*******************************************************************/
@ -42,6 +122,15 @@ void write_xml_circuit_model(std::fstream& fp,
}
fp << ">" << "\n";
/* Write the design technology of circuit model */
write_xml_design_technology(fp, fname, circuit_lib, model);
/* TODO: Write the ports of circuit model */
/* TODO: Write the wire parasticis of circuit model */
/* TODO: Write the delay matrix of circuit model */
/* Put an end to the XML definition of this circuit model */
fp << "\t\t" << "</circuit_model>\n";
}

1
libopenfpga/libarchopenfpga/src/write_xml_utils.cpp
View File

@ -22,4 +22,3 @@ void write_xml_attribute(std::fstream& fp,
fp << " " << attr << "=\"" << value << "\"";
}