From 0304d723c06e46899beaf155dbd06c19e5920da1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 16 Jan 2020 14:45:41 -0700 Subject: [PATCH] add XML writer for design technology of a circuit model --- .../libarchopenfpga/arch/sample_arch.xml | 84 +++++++------- .../libarchopenfpga/src/circuit_library.cpp | 103 ++++++++++++++++++ .../libarchopenfpga/src/circuit_library.h | 12 ++ .../libarchopenfpga/src/circuit_types.h | 26 +++-- .../src/read_xml_circuit_library.cpp | 13 ++- .../src/write_xml_circuit_library.cpp | 89 +++++++++++++++ .../libarchopenfpga/src/write_xml_utils.cpp | 1 - 7 files changed, 275 insertions(+), 53 deletions(-) diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml index 42367c98a..9a7f87ff3 100644 --- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml +++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml @@ -8,43 +8,18 @@ each primitives in FPGA architecture --> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + - + @@ -55,7 +30,7 @@ - + @@ -66,7 +41,7 @@ - + @@ -122,7 +97,7 @@ - + @@ -132,7 +107,7 @@ - + @@ -142,7 +117,7 @@ - + @@ -258,3 +233,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index 9dcfa62c8..4b02ca198 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -244,6 +244,24 @@ enum e_circuit_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(c return pass_gate_logic_types_[model_id]; } +/* Return the pmos size of a pass gate logic module, only applicable to circuit model whose type is pass-gate logic */ +float CircuitLibrary::pass_gate_logic_pmos_size(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be PASSGATE */ + VTR_ASSERT(CIRCUIT_MODEL_PASSGATE == model_type(model_id)); + return pass_gate_logic_sizes_[model_id].y(); +} + +/* Return the nmos size of a pass gate logic module, only applicable to circuit model whose type is pass-gate logic */ +float CircuitLibrary::pass_gate_logic_nmos_size(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be PASSGATE */ + VTR_ASSERT(CIRCUIT_MODEL_PASSGATE == model_type(model_id)); + return pass_gate_logic_sizes_[model_id].x(); +} + /* Return the type of multiplexing structure of a circuit model */ enum e_circuit_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const { /* validate the model_id */ @@ -305,6 +323,18 @@ bool CircuitLibrary::mux_use_local_encoder(const CircuitModelId& model_id) const return mux_use_local_encoder_[model_id]; } +/* Return if circuit model uses advanced RRAM design + * Only applicable for MUX/LUT circuit model + */ +bool CircuitLibrary::mux_use_advanced_rram_design(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT( (CIRCUIT_MODEL_MUX == model_type(model_id)) + || (CIRCUIT_MODEL_LUT == model_type(model_id)) ); + return mux_use_advanced_rram_design_[model_id]; +} + /* Return the type of gate for a circuit model * Only applicable for GATE circuit model */ @@ -327,6 +357,17 @@ enum e_circuit_model_buffer_type CircuitLibrary::buffer_type(const CircuitModelI return buffer_types_[model_id]; } +/* Return the size of buffer for a circuit model + * Only applicable for BUF/INV circuit model + */ +size_t CircuitLibrary::buffer_size(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is MUX */ + VTR_ASSERT(CIRCUIT_MODEL_INVBUF == model_type(model_id)); + return buffer_sizes_[model_id]; +} + /* Return the number of levels of buffer for a circuit model * Only applicable for BUF/INV circuit model */ @@ -338,6 +379,17 @@ size_t CircuitLibrary::buffer_num_levels(const CircuitModelId& model_id) const { return buffer_num_levels_[model_id]; } +/* Return the driving strength per level of buffer for a circuit model + * Only applicable for BUF/INV circuit model + */ +size_t CircuitLibrary::buffer_f_per_stage(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate the circuit model type is BUF */ + VTR_ASSERT(CIRCUIT_MODEL_INVBUF == model_type(model_id)); + return buffer_f_per_stage_[model_id]; +} + /* Find the circuit model id of the input buffer of a circuit model */ CircuitModelId CircuitLibrary::input_buffer_model(const CircuitModelId& model_id) const { /* validate the model_id */ @@ -369,6 +421,57 @@ size_t CircuitLibrary::num_delay_info(const CircuitModelId& model_id) const { return delay_types_[model_id].size(); } +/* Return the Low Resistance State Resistance of a RRAM model */ +float CircuitLibrary::rram_rlrs(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + return rram_res_[model_id].x(); +} + +/* Return the High Resistance State Resistance of a RRAM model */ +float CircuitLibrary::rram_rhrs(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + return rram_res_[model_id].y(); +} + +/* Return the size of PMOS transistor to set a RRAM model */ +float CircuitLibrary::rram_wprog_set_pmos(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + return wprog_set_[model_id].y(); +} + +float CircuitLibrary::rram_wprog_set_nmos(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + return wprog_set_[model_id].x(); +} + +float CircuitLibrary::rram_wprog_reset_pmos(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + return wprog_reset_[model_id].y(); +} + +float CircuitLibrary::rram_wprog_reset_nmos(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(CIRCUIT_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + return wprog_reset_[model_id].x(); +} + /************************************************************************ * Public Accessors : Basic data query on Circuit models' Circuit Port ***********************************************************************/ diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index 0005b9058..021be9b7a 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -198,21 +198,33 @@ class CircuitLibrary { /* Pass-gate-logic information */ CircuitModelId pass_gate_logic_model(const CircuitModelId& model_id) const; enum e_circuit_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; + float pass_gate_logic_pmos_size(const CircuitModelId& model_id) const; + float pass_gate_logic_nmos_size(const CircuitModelId& model_id) const; /* Multiplexer information */ enum e_circuit_model_structure mux_structure(const CircuitModelId& model_id) const; size_t mux_num_levels(const CircuitModelId& model_id) const; bool mux_add_const_input(const CircuitModelId& model_id) const; size_t mux_const_input_value(const CircuitModelId& model_id) const; bool mux_use_local_encoder(const CircuitModelId& model_id) const; + bool mux_use_advanced_rram_design(const CircuitModelId& model_id) const; /* Gate information */ enum e_circuit_model_gate_type gate_type(const CircuitModelId& model_id) const; /* Buffer information */ enum e_circuit_model_buffer_type buffer_type(const CircuitModelId& model_id) const; + size_t buffer_size(const CircuitModelId& model_id) const; size_t buffer_num_levels(const CircuitModelId& model_id) const; + size_t buffer_f_per_stage(const CircuitModelId& model_id) const; CircuitModelId input_buffer_model(const CircuitModelId& model_id) const; CircuitModelId output_buffer_model(const CircuitModelId& model_id) const; /* Delay information */ size_t num_delay_info(const CircuitModelId& model_id) const; + /* RRAM information */ + float rram_rlrs(const CircuitModelId& model_id) const; + float rram_rhrs(const CircuitModelId& model_id) const; + float rram_wprog_set_pmos(const CircuitModelId& model_id) const; + float rram_wprog_set_nmos(const CircuitModelId& model_id) const; + float rram_wprog_reset_pmos(const CircuitModelId& model_id) const; + float rram_wprog_reset_nmos(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on cirucit models' Circuit Ports*/ CircuitPortId model_port(const CircuitModelId& model_id, const std::string& name) const; size_t num_model_ports(const CircuitModelId& model_id) const; diff --git a/libopenfpga/libarchopenfpga/src/circuit_types.h b/libopenfpga/libarchopenfpga/src/circuit_types.h index 9c8d2a89a..151ca397a 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_types.h +++ b/libopenfpga/libarchopenfpga/src/circuit_types.h @@ -16,12 +16,6 @@ /* Header files should be included in a sequence */ /* Standard header files required go first */ -enum e_circuit_model_delay_type { - CIRCUIT_MODEL_DELAY_RISE, - CIRCUIT_MODEL_DELAY_FALL, - NUM_CIRCUIT_MODEL_DELAY_TYPES -}; - /*Struct for a CIRCUIT model of a module*/ enum e_circuit_model_type { CIRCUIT_MODEL_CHAN_WIRE, @@ -46,6 +40,8 @@ enum e_circuit_model_design_tech { CIRCUIT_MODEL_DESIGN_RRAM, NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES }; +/* Strings correspond to each design technology type */ +constexpr std::array CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING = {{"cmos", "rram"}}; enum e_circuit_model_structure { CIRCUIT_MODEL_STRUCTURE_TREE, @@ -55,13 +51,15 @@ enum e_circuit_model_structure { NUM_CIRCUIT_MODEL_STRUCTURE_TYPES }; /* Strings correspond to each type of mux structure */ -constexpr std::array CIRCUIT_MODEL_STRUCTURE_TYPE_STRING = {{"TREE-LIKE", "ONE-LEVEL", "MULTI-LEVEL", "CROSSBAR"}}; +constexpr std::array CIRCUIT_MODEL_STRUCTURE_TYPE_STRING = {{"tree", "one_level", "multi_level", "crossbar"}}; enum e_circuit_model_buffer_type { CIRCUIT_MODEL_BUF_INV, CIRCUIT_MODEL_BUF_BUF, NUM_CIRCUIT_MODEL_BUF_TYPES }; +/* Strings correspond to each type of buffer */ +constexpr std::array CIRCUIT_MODEL_BUFFER_TYPE_STRING = {{"inverter", "buffer"}}; enum e_circuit_model_pass_gate_logic_type { CIRCUIT_MODEL_PASS_GATE_TRANSMISSION, @@ -70,6 +68,8 @@ enum e_circuit_model_pass_gate_logic_type { CIRCUIT_MODEL_PASS_GATE_STDCELL, /* Standard cell as a special type of pass-gate logic */ NUM_CIRCUIT_MODEL_PASS_GATE_TYPES }; +/* Strings correspond to each type of buffer */ +constexpr std::array CIRCUIT_MODEL_PASSGATE_TYPE_STRING = {{"transmission_gate", "pass_transistor", "rram", "standard_cell"}}; enum e_circuit_model_gate_type { CIRCUIT_MODEL_GATE_AND, @@ -77,6 +77,8 @@ enum e_circuit_model_gate_type { CIRCUIT_MODEL_GATE_MUX2, NUM_CIRCUIT_MODEL_GATE_TYPES }; +/* Strings correspond to each type of logic gate */ +constexpr std::array CIRCUIT_MODEL_GATE_TYPE_STRING = {{"AND", "OR", "MUX2"}}; enum e_wire_model_type { WIRE_MODEL_PI, @@ -97,7 +99,13 @@ enum e_circuit_model_port_type { NUM_CIRCUIT_MODEL_PORT_TYPES }; /* Strings correspond to each port type */ -constexpr std::array CIRCUIT_MODEL_PORT_TYPE_STRING = {{"INPUT", "OUTPUT", "INOUT", "CLOCK", "SRAM", "BL", "BLB", "WL", "WLB"}}; +constexpr std::array CIRCUIT_MODEL_PORT_TYPE_STRING = {{"input", "output", "inout", "clock", "sram", "bl", "blb", "wl", "wlb"}}; + +enum e_circuit_model_delay_type { + CIRCUIT_MODEL_DELAY_RISE, + CIRCUIT_MODEL_DELAY_FALL, + NUM_CIRCUIT_MODEL_DELAY_TYPES +}; /* For SRAM */ enum e_sram_orgz { @@ -108,6 +116,6 @@ enum e_sram_orgz { NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES }; -constexpr std::array CIRCUIT_MODEL_SRAM_ORGZ_TYPE_STRING = {{"STANDALONE", "SCAN-CHAIN", "MEMORY_BANK", "LOCAL_ENCODER"}}; +constexpr std::array CIRCUIT_MODEL_SRAM_ORGZ_TYPE_STRING = {{"standalone", "scan_chain", "memory_bank", "local_encoder"}}; #endif diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index fb26c49bc..b5a514bfb 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -135,11 +135,11 @@ e_circuit_model_structure string_to_mux_structure_type(const std::string& type_s return CIRCUIT_MODEL_STRUCTURE_TREE; } - if (std::string("one-level") == type_string) { + if (std::string("one_level") == type_string) { return CIRCUIT_MODEL_STRUCTURE_ONELEVEL; } - if (std::string("multi-level") == type_string) { + if (std::string("multi_level") == type_string) { return CIRCUIT_MODEL_STRUCTURE_MULTILEVEL; } @@ -289,7 +289,7 @@ void read_xml_model_design_technology(pugi::xml_node& xml_model, * 3. driving strength per stage */ circuit_lib.set_buffer_size(model, get_attribute(xml_design_tech, "size", loc_data).as_float(0.)); - circuit_lib.set_buffer_num_levels(model, get_attribute(xml_design_tech, "tap_drive_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0)); + circuit_lib.set_buffer_num_levels(model, get_attribute(xml_design_tech, "num_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(1)); circuit_lib.set_buffer_f_per_stage(model, get_attribute(xml_design_tech, "f_per_stage", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(4)); } @@ -358,6 +358,13 @@ void read_xml_model_design_technology(pugi::xml_node& xml_model, } if (CIRCUIT_MODEL_STRUCTURE_MULTILEVEL == circuit_lib.mux_structure(model)) { circuit_lib.set_mux_num_levels(model, get_attribute(xml_design_tech, "num_level", loc_data).as_int(1)); + /* Correction on the mux structure: + * if the number of level is set to 1 in a multi-level multiplexer, + * we change the mux structure to one-level + */ + if (1 == circuit_lib.mux_num_levels(model)) { + circuit_lib.set_mux_structure(model, CIRCUIT_MODEL_STRUCTURE_ONELEVEL); + } } circuit_lib.set_mux_use_advanced_rram_design(model, get_attribute(xml_design_tech, "advanced_rram_design", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); circuit_lib.set_mux_use_local_encoder(model, get_attribute(xml_design_tech, "local_encoder", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index 39084cdf3..146fe381d 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -12,6 +12,86 @@ #include "write_xml_utils.h" #include "write_xml_circuit_library.h" +/******************************************************************** + * A writer to output the design technology of a circuit model to XML format + *******************************************************************/ +static +void write_xml_design_technology(std::fstream& fp, + const char* fname, + const CircuitLibrary& circuit_lib, + const CircuitModelId& model) { + /* Validate the file stream */ + openfpga::check_file_stream(fname, fp); + + fp << "\t\t\t" << "" << "\n"; + return; +} + /******************************************************************** * A writer to output a circuit model to XML format *******************************************************************/ @@ -42,6 +122,15 @@ void write_xml_circuit_model(std::fstream& fp, } fp << ">" << "\n"; + /* Write the design technology of circuit model */ + write_xml_design_technology(fp, fname, circuit_lib, model); + + /* TODO: Write the ports of circuit model */ + + /* TODO: Write the wire parasticis of circuit model */ + + /* TODO: Write the delay matrix of circuit model */ + /* Put an end to the XML definition of this circuit model */ fp << "\t\t" << "\n"; } diff --git a/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp b/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp index efb5e97a0..b7b02b272 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_utils.cpp @@ -22,4 +22,3 @@ void write_xml_attribute(std::fstream& fp, fp << " " << attr << "=\"" << value << "\""; } -