Merge pull request #1645 from lnis-uofu/xt_fhie

Flexible outputs on command write_fabric_hierarchy

docs/source/manual/file_formats/fabric_hierarchy_file.rst

@@ -0,0 +1,62 @@
+.. _file_format_fabric_hierarchy_file:
+
+Fabric Hierarchy File (.yaml)
+----------------------------------------
+
+This file is generated by command :ref:`openfpga_setup_commands_write_fabric_hierarchy`
+
+
+The fabric hierarchy file aims to show module trees of a number of given roots
+
+This file is created for netlist manipulation and detailed floorplanning during physical design steps
+
+By using the options of the command :ref:`openfpga_setup_commands_write_fabric_hierarchy`, user can selectively output the module tree on their needs.
+
+An example of the file is shown as follows.
+
+.. code-block:: yaml
+
+  fpga_top:
+    tile_0__2_:
+      sb_0__1_:
+        mux_tree_tapbuf_size2:
+          INVTX1
+          const1
+          tap_buf4
+          mux_tree_tapbuf_basis_input2_mem1:
+            - TGATE
+        mux_tree_tapbuf_size2_feedthrough_mem
+        sb_1__config_group_mem_size40:
+          mux_tree_tapbuf_size2_mem:
+            - DFF
+    tile_1__2_:
+      grid_io_top:
+        logical_tile_io_mode_io_:
+          logical_tile_io_mode_physical__iopad:
+            - GPIO
+            - GPIO_feedthrough_DFF_mem
+          direct_interc
+
+In this example, the root module is ``fpga_top``.
+The child modules under ``fpga_top`` are ``tile_0__2_`` and ``tile_1__2_``.
+Note that the leaf nodes are shown as a list, e.g., ``GPIO`` and ``GPIO_feedthrough_DFF_mem``.
+
+When multiple root modules are defined, the output could be
+
+.. code-block:: yaml
+
+  sb_0__1_:
+    - mux_tree_tapbuf_size2
+  sb_1__0_:
+    - mux_tree_tapbuf_size2
+  sb_1__1_:
+    - mux_tree_tapbuf_size2
+  cbx_1__0_:
+    - mux_tree_tapbuf_size4
+  cbx_1__1_:
+    - mux_tree_tapbuf_size4
+  cby_0__1_:
+    - mux_tree_tapbuf_size2
+    - mux_tree_tapbuf_size4
+  cby_1__1_:
+    - mux_tree_tapbuf_size4

docs/source/manual/file_formats/index.rst

@@ -43,3 +43,5 @@ OpenFPGA widely uses XML format for interchangeable files
    tile_config_file
 
    fabric_pin_physical_location_file
+
+   fabric_hierarchy_file

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -359,20 +359,33 @@ add_fpga_core_to_fabric
 
     Show verbose log
 
+.. _openfpga_setup_commands_write_fabric_hierarchy:
 
 write_fabric_hierarchy
 ~~~~~~~~~~~~~~~~~~~~~~
 
-  Write the hierarchy of FPGA fabric graph to a plain-text file
+  Write the hierarchy of FPGA fabric graph to a YAML file
   
   .. option:: --file <string> or -f <string>
   
-    Specify the file name to write the hierarchy. 
+    Specify the file name to write the hierarchy.  See details in :ref:`file_format_fabric_hierarchy_file`.
 
   .. option:: --depth <int>
 
     Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1. 
 
+  .. option:: --module <regexp>
+
+    Specify the root module name(s) which should be considered. By default, it is ``fpga_top``. Note that regular expression is supported. For example, ``grid_*`` will output all the modules with a prefix of ``grid_``
+
+  .. option:: --filter <regexp>
+
+    Specify the filter which allows user to select modules to appear under each root module tree. By default, it is ``*``. Regular expression is supported. For example, ``*mux*`` will output all the modules which contains ``mux``. In the other words, the filter defines a white list.
+
+  .. option:: --exclude_empty_modules
+
+    Exclude modules with no qualified children (match the names defined through filter) from the output file
+
   .. option:: --verbose
 
     Show verbose log

openfpga/src/base/openfpga_build_fabric_template.h

@@ -270,6 +270,8 @@ template <class T>
 int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd,
                                     const CommandContext& cmd_context) {
   CommandOptionId opt_verbose = cmd.option("verbose");
+  CommandOptionId opt_exclude_empty_modules =
+    cmd.option("exclude_empty_modules");
 
   /* Check the option '--file' is enabled or not
    * Actually, it must be enabled as the shell interface will check
@@ -279,6 +281,19 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd,
   VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
   VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
 
+  CommandOptionId opt_module = cmd.option("module");
+  std::string root_module =
+    openfpga_ctx.module_name_map().name(generate_fpga_top_module_name());
+  if (true == cmd_context.option_enable(cmd, opt_module)) {
+    root_module = cmd_context.option_value(cmd, opt_module);
+  }
+
+  CommandOptionId opt_filter = cmd.option("filter");
+  std::string filter("*");
+  if (true == cmd_context.option_enable(cmd, opt_filter)) {
+    filter = cmd_context.option_value(cmd, opt_filter);
+  }
+
   /* Default depth requirement, will not stop until the leaf */
   int depth = -1;
   CommandOptionId opt_depth = cmd.option("depth");
@@ -297,7 +312,9 @@ int write_fabric_hierarchy_template(const T& openfpga_ctx, const Command& cmd,
   /* Write hierarchy to a file */
   return write_fabric_hierarchy_to_text_file(
     openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), hie_file_name,
-    size_t(depth), cmd_context.option_enable(cmd, opt_verbose));
+    root_module, filter, size_t(depth),
+    cmd_context.option_enable(cmd, opt_exclude_empty_modules),
+    cmd_context.option_enable(cmd, opt_verbose));
 }
 
 /********************************************************************

openfpga/src/base/openfpga_setup_command_template.h

@@ -461,12 +461,29 @@ ShellCommandId add_write_fabric_hierarchy_command_template(
   shell_cmd.set_option_short_name(opt_file, "f");
   shell_cmd.set_option_require_value(opt_file, openfpga::OPT_STRING);
 
+  /* Add an option '--module' */
+  CommandOptionId opt_module = shell_cmd.add_option(
+    "module", false,
+    "Specify the root module name(s) which should be considered. By default, "
+    "it is fpga_top. Regular expression is supported");
+  shell_cmd.set_option_require_value(opt_module, openfpga::OPT_STRING);
+  CommandOptionId opt_filter =
+    shell_cmd.add_option("filter", false,
+                         "Specify the filter which allows user to select "
+                         "modules to appear under each root module tree. By "
+                         "default, it is *. Regular expression is supported");
+  shell_cmd.set_option_require_value(opt_filter, openfpga::OPT_STRING);
+
   /* Add an option '--depth' */
   CommandOptionId opt_depth = shell_cmd.add_option(
     "depth", false,
     "Specify the depth of hierarchy to which the writer should stop");
   shell_cmd.set_option_require_value(opt_depth, openfpga::OPT_INT);
 
+  shell_cmd.add_option("exclude_empty_modules", false,
+                       "Exclude modules with no qualified children (match the "
+                       "names defined through filter) from the output file");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Show verbose outputs");
 

openfpga/src/fabric/fabric_hierarchy_writer.cpp

@@ -1,12 +1,14 @@
 /***************************************************************************************
  * Output internal structure of Module Graph hierarchy to file formats
  ***************************************************************************************/
+#include <regex>
 /* Headers from vtrutil library */
 #include "vtr_assert.h"
 #include "vtr_log.h"
 #include "vtr_time.h"
 
 /* Headers from openfpgautil library */
+#include "command_exit_codes.h"
 #include "fabric_hierarchy_writer.h"
 #include "openfpga_digest.h"
 #include "openfpga_naming.h"
@@ -14,6 +16,32 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/** Identify if the module has no child whose name matches the filter */
+static bool module_filter_all_children(const ModuleManager& module_manager,
+                                       const ModuleId& curr_module,
+                                       const ModuleNameMap& module_name_map,
+                                       const std::string& module_name_filter) {
+  for (const ModuleId& child_module :
+       module_manager.child_modules(curr_module)) {
+    /* Filter out the names which do not match the pattern */
+    std::string child_module_name = module_manager.module_name(child_module);
+    if (module_name_map.name_exist(child_module_name)) {
+      child_module_name = module_name_map.name(child_module_name);
+    }
+    std::string pattern = module_name_filter;
+    std::regex star_replace("\\*");
+    std::regex questionmark_replace("\\?");
+    std::string wildcard_pattern =
+      std::regex_replace(std::regex_replace(pattern, star_replace, ".*"),
+                         questionmark_replace, ".");
+    std::regex wildcard_regex(wildcard_pattern);
+    if (std::regex_match(child_module_name, wildcard_regex)) {
+      return false;
+    }
+  }
+  return true;
+}
+
 /***************************************************************************************
  * Recursively output child module of the parent_module to a text file
  * We use Depth-First Search (DFS) here so that we can output a tree down to
@@ -23,52 +51,88 @@ namespace openfpga {
 static int rec_output_module_hierarchy_to_text_file(
   std::fstream& fp, const size_t& hie_depth_to_stop,
   const size_t& current_hie_depth, const ModuleManager& module_manager,
-  const ModuleId& parent_module, const bool& verbose) {
+  const ModuleId& parent_module, const ModuleNameMap& module_name_map,
+  const std::string& module_name_filter, const bool& verbose) {
   /* Stop if hierarchy depth is beyond the stop line */
   if (hie_depth_to_stop < current_hie_depth) {
-    return 0;
+    return CMD_EXEC_SUCCESS;
   }
 
   if (false == valid_file_stream(fp)) {
-    return 2;
+    return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* Check if all the child module has not qualified grand-child, use leaf for
+   * this level */
+  bool use_list = true;
+  for (const ModuleId& child_module :
+       module_manager.child_modules(parent_module)) {
+    if (!module_filter_all_children(module_manager, child_module,
+                                    module_name_map, module_name_filter)) {
+      use_list = false;
+      break;
+    }
+  }
+  /* For debug use only
+  VTR_LOGV(verbose, "Current depth: %lu, Target depth: %lu\n",
+           current_hie_depth, hie_depth_to_stop);
+  */
+  std::string parent_module_name = module_manager.module_name(parent_module);
+  if (module_name_map.name_exist(parent_module_name)) {
+    parent_module_name = module_name_map.name(parent_module_name);
+  }
+  VTR_LOGV(
+    use_list && verbose, "Use list as module '%s' contains only leaf nodes\n",
+    module_name_map.name(module_manager.module_name(parent_module)).c_str());
+
   /* Iterate over all the child module */
   for (const ModuleId& child_module :
        module_manager.child_modules(parent_module)) {
-    if (false == write_space_to_file(fp, current_hie_depth * 2)) {
-      return 2;
-    }
-
     if (true != module_manager.valid_module_id(child_module)) {
-      VTR_LOGV_ERROR(verbose, "Unable to find the child module '%u'!\n",
-                     size_t(child_module));
-      return 1;
+      VTR_LOGV_ERROR(
+        verbose,
+        "Unable to find the child module '%s' under its parent '%s'!\n",
+        module_manager.module_name(child_module).c_str(),
+        module_manager.module_name(parent_module).c_str());
+      return CMD_EXEC_FATAL_ERROR;
     }
 
-    fp << "- ";
-    fp << module_manager.module_name(child_module);
-
-    /* If this is the leaf node, we leave a new line
-     * Otherwise, we will leave a ':' to be compatible to YAML file format
-     */
-    if ((0 != module_manager.child_modules(child_module).size()) &&
-        (hie_depth_to_stop >= current_hie_depth + 1)) {
-      fp << ":";
+    /* Filter out the names which do not match the pattern */
+    std::string child_module_name = module_manager.module_name(child_module);
+    if (module_name_map.name_exist(child_module_name)) {
+      child_module_name = module_name_map.name(child_module_name);
+    }
+    std::string pattern = module_name_filter;
+    std::regex star_replace("\\*");
+    std::regex questionmark_replace("\\?");
+    std::string wildcard_pattern =
+      std::regex_replace(std::regex_replace(pattern, star_replace, ".*"),
+                         questionmark_replace, ".");
+    std::regex wildcard_regex(wildcard_pattern);
+    if (!std::regex_match(child_module_name, wildcard_regex)) {
+      continue;
     }
-    fp << "\n";
 
+    if (false == write_space_to_file(fp, current_hie_depth * 2)) {
+      return CMD_EXEC_FATAL_ERROR;
+    }
+    if (hie_depth_to_stop == current_hie_depth || use_list) {
+      fp << "- " << child_module_name.c_str() << "\n";
+    } else {
+      fp << child_module_name.c_str() << ":\n";
+    }
     /* Go to next level */
     int status = rec_output_module_hierarchy_to_text_file(
       fp, hie_depth_to_stop,
       current_hie_depth + 1, /* Increment the depth for the next level */
-      module_manager, child_module, verbose);
-    if (0 != status) {
+      module_manager, child_module, module_name_map, module_name_filter,
+      verbose);
+    if (status != CMD_EXEC_SUCCESS) {
       return status;
     }
   }
 
-  return 0;
+  return CMD_EXEC_SUCCESS;
 }
 
 /***************************************************************************************
@@ -83,11 +147,11 @@ static int rec_output_module_hierarchy_to_text_file(
  * Return 1 if there are more serious bugs in the architecture
  * Return 2 if fail when creating files
  ***************************************************************************************/
-int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
-                                        const ModuleNameMap& module_name_map,
-                                        const std::string& fname,
-                                        const size_t& hie_depth_to_stop,
-                                        const bool& verbose) {
+int write_fabric_hierarchy_to_text_file(
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const std::string& fname, const std::string& root_module_names,
+  const std::string& module_name_filter, const size_t& hie_depth_to_stop,
+  const bool& exclude_empty_modules, const bool& verbose) {
   std::string timer_message =
     std::string("Write fabric hierarchy to plain-text file '") + fname +
     std::string("'");
@@ -111,35 +175,61 @@ int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
   /* Validate the file stream */
   check_file_stream(fname.c_str(), fp);
 
-  /* Find top-level module */
-  std::string top_module_name =
-    module_name_map.name(generate_fpga_top_module_name());
-  ModuleId top_module = module_manager.find_module(top_module_name);
-  if (true != module_manager.valid_module_id(top_module)) {
-    VTR_LOGV_ERROR(verbose, "Unable to find the top-level module '%s'!\n",
-                   top_module_name.c_str());
-    return 1;
+  size_t cnt = 0;
+  /* Use regular expression to capture the module whose name matches the pattern
+   */
+  for (ModuleId curr_module : module_manager.modules()) {
+    std::string curr_module_name = module_manager.module_name(curr_module);
+    if (module_name_map.name_exist(curr_module_name)) {
+      curr_module_name = module_name_map.name(curr_module_name);
+    }
+    std::string pattern = root_module_names;
+    std::regex star_replace("\\*");
+    std::regex questionmark_replace("\\?");
+    std::string wildcard_pattern =
+      std::regex_replace(std::regex_replace(pattern, star_replace, ".*"),
+                         questionmark_replace, ".");
+    std::regex wildcard_regex(wildcard_pattern);
+    if (!std::regex_match(curr_module_name, wildcard_regex)) {
+      continue;
+    }
+    /* Filter out module without children if required */
+    if (exclude_empty_modules &&
+        module_filter_all_children(module_manager, curr_module, module_name_map,
+                                   module_name_filter)) {
+      continue;
+    }
+    VTR_LOGV(verbose, "Select module '%s' as root\n", curr_module_name.c_str());
+    /* Record current depth of module: top module is the root with 0 depth */
+    size_t hie_depth = 0;
+
+    fp << curr_module_name << ":"
+       << "\n";
+
+    /* Visit child module recursively and output the hierarchy */
+    int err_code = rec_output_module_hierarchy_to_text_file(
+      fp, hie_depth_to_stop, hie_depth + 1, /* Start with level 1 */
+      module_manager, curr_module, module_name_map, module_name_filter,
+      verbose);
+    /* Catch error code and exit if required */
+    if (err_code == CMD_EXEC_FATAL_ERROR) {
+      return err_code;
+    }
+    cnt++;
   }
 
-  /* Record current depth of module: top module is the root with 0 depth */
-  size_t hie_depth = 0;
-
-  if (hie_depth_to_stop < hie_depth) {
-    return 0;
+  if (cnt == 0) {
+    VTR_LOG_ERROR(
+      "Unable to find any module matching the root module name pattern '%s'!\n",
+      root_module_names.c_str());
+    return CMD_EXEC_FATAL_ERROR;
   }
-
-  fp << top_module_name << ":"
-     << "\n";
-
-  /* Visit child module recursively and output the hierarchy */
-  int err_code = rec_output_module_hierarchy_to_text_file(
-    fp, hie_depth_to_stop, hie_depth + 1, /* Start with level 1 */
-    module_manager, top_module, verbose);
+  VTR_LOG("Outputted %lu modules as root\n", cnt);
 
   /* close a file */
   fp.close();
 
-  return err_code;
+  return CMD_EXEC_SUCCESS;
 }
 
 } /* end namespace openfpga */

openfpga/src/fabric/fabric_hierarchy_writer.h

@@ -14,11 +14,11 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-int write_fabric_hierarchy_to_text_file(const ModuleManager& module_manager,
-                                        const ModuleNameMap& module_name_map,
-                                        const std::string& fname,
-                                        const size_t& hie_depth_to_stop,
-                                        const bool& verbose);
+int write_fabric_hierarchy_to_text_file(
+  const ModuleManager& module_manager, const ModuleNameMap& module_name_map,
+  const std::string& fname, const std::string& root_module_names,
+  const std::string& module_name_filter, const size_t& hie_depth_to_stop,
+  const bool& exclude_empty_modules, const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga

@@ -30,7 +30,8 @@ ${OPENFPGA_ADD_FPGA_CORE_MODULE}
 
 # Write the fabric hierarchy of module graph to a file
 # This is used by hierarchical PnR flows
-write_fabric_hierarchy --file ./fabric_hierarchy.txt
+write_fabric_hierarchy --file ./config_mem.yaml --depth 1 --module * --filter *config_group_mem* --verbose --exclude_empty_modules
+write_fabric_hierarchy --file ./mux_modules.txt --depth 1 --module (grid|cbx|cby|sb)* --filter *mux*_size([0-9]+) --verbose --exclude_empty_modules
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation

openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga

@@ -27,7 +27,7 @@ build_fabric --compress_routing #--verbose
 
 # Write the fabric hierarchy of module graph to a file
 # This is used by hierarchical PnR flows
-write_fabric_hierarchy --file ./fabric_hierarchy.txt
+write_fabric_hierarchy --file ${OPENFPGA_OUTPUT_DIR}/mux_modules.yaml --depth 1 --module (grid|cbx|cby|sb)* --filter *mux*_size([0-9]+) --verbose --exclude_empty_modules
 
 # Write the fabric I/O attributes to a file
 # This is used by pin constraint files

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/mux_modules.yaml

@@ -0,0 +1,24 @@
+sb_0__0_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_0__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_1__0_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_1__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+cbx_1__0_:
+  - mux_tree_tapbuf_size6
+cbx_1__1_:
+  - mux_tree_tapbuf_size6
+cby_0__1_:
+  - mux_tree_tapbuf_size6
+cby_1__1_:
+  - mux_tree_tapbuf_size6

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/mux_modules.yaml

@@ -0,0 +1,55 @@
+sb_0__0_:
+  - mux_tree_tapbuf_size2
+sb_0__1_:
+  - mux_tree_tapbuf_size9
+  - mux_tree_tapbuf_size8
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_0__4_:
+  - mux_tree_tapbuf_size2
+sb_1__0_:
+  - mux_tree_tapbuf_size5
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size9
+  - mux_tree_tapbuf_size8
+  - mux_tree_tapbuf_size10
+sb_1__1_:
+  - mux_tree_tapbuf_size11
+  - mux_tree_tapbuf_size9
+  - mux_tree_tapbuf_size10
+  - mux_tree_tapbuf_size8
+sb_1__4_:
+  - mux_tree_tapbuf_size9
+  - mux_tree_tapbuf_size8
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_4__0_:
+  - mux_tree_tapbuf_size2
+sb_4__1_:
+  - mux_tree_tapbuf_size10
+  - mux_tree_tapbuf_size8
+  - mux_tree_tapbuf_size9
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_4__4_:
+  - mux_tree_tapbuf_size2
+cbx_1__0_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size2
+cbx_1__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size2
+cbx_1__4_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size2
+cby_0__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size2
+cby_1__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size2
+cby_4__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size2

openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/mux_modules.yaml

@@ -0,0 +1,24 @@
+sb_0__0_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_0__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_1__0_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+sb_1__1_:
+  - mux_tree_tapbuf_size4
+  - mux_tree_tapbuf_size3
+  - mux_tree_tapbuf_size2
+cbx_1__0_:
+  - mux_tree_tapbuf_size6
+cbx_1__1_:
+  - mux_tree_tapbuf_size6
+cby_0__1_:
+  - mux_tree_tapbuf_size6
+cby_1__1_:
+  - mux_tree_tapbuf_size6

openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/mux_modules.yaml

@@ -0,0 +1,54 @@
+sb_0__0_:
+  - mux_2level_tapbuf_size2
+  - mux_2level_tapbuf_size3
+sb_0__1_:
+  - mux_2level_tapbuf_size9
+  - mux_2level_tapbuf_size8
+  - mux_2level_tapbuf_size3
+  - mux_2level_tapbuf_size4
+  - mux_2level_tapbuf_size2
+  - mux_2level_tapbuf_size7
+sb_0__2_:
+  - mux_2level_tapbuf_size2
+sb_1__0_:
+  - mux_2level_tapbuf_size5
+  - mux_2level_tapbuf_size4
+  - mux_2level_tapbuf_size3
+  - mux_2level_tapbuf_size2
+  - mux_2level_tapbuf_size10
+  - mux_2level_tapbuf_size9
+  - mux_2level_tapbuf_size11
+sb_1__1_:
+  - mux_2level_tapbuf_size13
+  - mux_2level_tapbuf_size9
+sb_1__2_:
+  - mux_2level_tapbuf_size9
+  - mux_2level_tapbuf_size7
+  - mux_2level_tapbuf_size4
+  - mux_2level_tapbuf_size3
+  - mux_2level_tapbuf_size2
+sb_2__0_:
+  - mux_2level_tapbuf_size3
+  - mux_2level_tapbuf_size2
+sb_2__1_:
+  - mux_2level_tapbuf_size11
+  - mux_2level_tapbuf_size9
+  - mux_2level_tapbuf_size10
+  - mux_2level_tapbuf_size4
+  - mux_2level_tapbuf_size2
+sb_2__2_:
+  - mux_2level_tapbuf_size3
+  - mux_2level_tapbuf_size2
+cbx_1__0_:
+  - mux_2level_tapbuf_size2
+  - mux_2level_tapbuf_size4
+cbx_1__1_:
+  - mux_2level_tapbuf_size2
+cbx_1__2_:
+  - mux_2level_tapbuf_size4
+cby_0__1_:
+  - mux_2level_tapbuf_size4
+cby_1__1_:
+  - mux_2level_tapbuf_size4
+cby_2__1_:
+  - mux_2level_tapbuf_size4