54 lines
1.3 KiB
Coq
54 lines
1.3 KiB
Coq
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//-----------------------------------------------------
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// Design Name : MUX2
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// File Name : mux2.v
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// Function : Standard cell (static gate) implementation
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// of 2-input multiplexers
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// Coder : Xifan Tang
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//-----------------------------------------------------
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module MUX2(
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input A, // Data input 0
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input B, // Data input 1
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input S0, // Select port
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output Y // Data output
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);
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assign Y = S0 ? B : A;
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// Note:
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// MUX2 appears will appear in LUTs, routing multiplexers,
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// being a component in combinational loops
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// To help convergence in simulation
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// i.e., to avoid the X (undetermined) signals,
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// the following timing constraints and signal initialization
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// has to be added!
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`ifdef ENABLE_TIMING
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// ------ BEGIN Pin-to-pin Timing constraints -----
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specify
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(A => Y) = (0.001, 0.001);
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(B => Y) = (0.001, 0.001);
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(S0 => Y) = (0.001, 0.001);
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endspecify
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// ------ END Pin-to-pin Timing constraints -----
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`endif
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`ifdef ENABLE_SIGNAL_INITIALIZATION
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// ------ BEGIN driver initialization -----
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initial begin
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`ifdef ENABLE_FORMAL_VERIFICATION
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$deposit(A, 1'b0);
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$deposit(B, 1'b0);
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$deposit(S0, 1'b0);
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`else
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$deposit(A, $random);
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$deposit(B, $random);
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$deposit(S0, $random);
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`endif
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end
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// ------ END driver initialization -----
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`endif
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endmodule
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