2018-10-18 17:28:12 -05:00
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Extended Architecture Description Language
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==========================================
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2018-09-25 15:53:04 -05:00
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2018-09-13 16:38:41 -05:00
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.. _arch_lang:
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Extended FPGA Architecture Description Language
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.. toctree::
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:maxdepth: 2
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2018-09-13 23:58:54 -05:00
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generality
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2019-09-30 11:00:46 -05:00
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interconnect
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2018-09-13 23:58:54 -05:00
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spice_sim_setting
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tech_lib
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2018-09-13 16:38:41 -05:00
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2018-09-13 23:58:54 -05:00
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circuit_modules
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2018-09-13 16:38:41 -05:00
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2018-12-03 11:58:50 -06:00
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circuit_model_examples
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2018-09-13 23:58:54 -05:00
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link_circuit_modules
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2018-09-13 16:38:41 -05:00
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