2020-02-16 15:47:54 -06:00
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#ifndef VERILOG_ROUTING_H
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#define VERILOG_ROUTING_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "mux_library.h"
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#include "module_manager.h"
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2020-04-23 21:42:11 -05:00
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#include "netlist_manager.h"
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2020-02-16 15:47:54 -06:00
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#include "device_rr_gsb.h"
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2021-02-28 12:57:40 -06:00
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#include "fabric_verilog_options.h"
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2020-02-16 15:47:54 -06:00
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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2020-04-23 21:42:11 -05:00
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void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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2020-02-16 15:47:54 -06:00
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const DeviceRRGSB& device_rr_gsb,
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const std::string& subckt_dir,
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const FabricVerilogOption& options);
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2020-02-16 15:47:54 -06:00
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2020-04-23 21:42:11 -05:00
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void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
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const ModuleManager& module_manager,
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2020-02-16 15:47:54 -06:00
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const DeviceRRGSB& device_rr_gsb,
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const std::string& subckt_dir,
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2021-02-28 12:57:40 -06:00
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const FabricVerilogOption& options);
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2020-02-16 15:47:54 -06:00
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} /* end namespace openfpga */
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#endif
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