2019-09-12 21:49:02 -05:00
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/***********************************************
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* Header file for verilog_wire.cpp
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**********************************************/
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#ifndef VERILOG_WIRE_H
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#define VERILOG_WIRE_H
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/* Include other header files which are dependency on the function declared below */
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#include <fstream>
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#include <vector>
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "circuit_library.h"
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#include "module_manager.h"
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void print_verilog_submodule_wires(ModuleManager& module_manager,
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2019-12-04 18:55:05 -06:00
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std::vector<std::string>& netlist_names,
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2019-09-12 21:49:02 -05:00
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir);
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#endif
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