2019-06-08 21:11:22 -05:00
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#ifndef VERILOG_SDC_H
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#define VERILOG_SDC_H
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2019-04-26 13:23:47 -05:00
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void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,
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char* sdc_dir,
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t_arch arch,
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t_det_routing_arch* routing_arch,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices,
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t_rr_indexed_data* LL_rr_indexed_data,
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2019-06-10 13:50:10 -05:00
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int LL_nx, int LL_ny, DeviceRRGSB& LL_device_rr_gsb,
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2019-06-10 11:57:26 -05:00
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boolean compact_routing_hierarchy);
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2019-04-26 13:23:47 -05:00
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void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info,
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char* sdc_dir,
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t_arch arch,
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int LL_num_rr_nodes, t_rr_node* LL_rr_node,
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t_ivec*** LL_rr_node_indices,
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int LL_nx, int LL_ny, t_grid_tile** LL_grid,
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2019-06-10 13:50:10 -05:00
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t_block* LL_block, DeviceRRGSB& LL_device_rr_gsb,
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2019-05-24 16:10:08 -05:00
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boolean compact_routing_hierarchy);
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2019-04-26 13:23:47 -05:00
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void dump_sdc_one_clb_muxes(FILE* fp,
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2019-05-24 16:10:08 -05:00
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char* grid_instance_name,
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t_rr_graph* rr_graph,
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t_pb_graph_node* pb_graph_head);
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2019-04-26 13:23:47 -05:00
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void dump_sdc_rec_one_pb_muxes(FILE* fp,
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2019-05-24 16:10:08 -05:00
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char* grid_instance_name,
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t_rr_graph* rr_graph,
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t_pb_graph_node* cur_pb_graph_node);
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2019-04-26 13:23:47 -05:00
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void dump_sdc_pb_graph_node_muxes(FILE* fp,
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char* grid_instance_name,
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t_rr_graph* rr_graph,
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t_pb_graph_node* cur_pb_graph_node);
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2019-05-24 16:10:08 -05:00
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void dump_sdc_pb_graph_pin_muxes(FILE* fp,
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char* grid_instance_name,
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t_rr_graph* rr_graph,
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t_pb_graph_pin pb_graph_pin);
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2019-04-26 13:23:47 -05:00
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2019-06-08 21:11:22 -05:00
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#endif
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