OpenFPGA/libs/libnamemanager/example/example_module_names.xml

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<module_names>
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<module_name default="tile_0__1_" given="tile_io_bottom"/>
<module_name default="tile_1__1_" given="tile_clb"/>
<module_name default="tile_1__0_" given="tile_io_left"/>
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</module_names>