2020-02-16 13:21:59 -06:00
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#ifndef VERILOG_DECODERS_H
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#define VERILOG_DECODERS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include <string>
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#include <vector>
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#include "circuit_library.h"
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2020-05-27 15:25:06 -05:00
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#include "decoder_library.h"
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2022-10-06 19:08:50 -05:00
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#include "fabric_verilog_options.h"
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2020-02-16 13:21:59 -06:00
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#include "module_manager.h"
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#include "mux_graph.h"
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#include "mux_library.h"
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2020-04-23 21:42:11 -05:00
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#include "netlist_manager.h"
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2021-02-28 12:57:40 -06:00
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#include "verilog_port_types.h"
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2020-02-16 13:21:59 -06:00
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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2022-10-06 19:08:50 -05:00
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void print_verilog_submodule_mux_local_decoders(
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const ModuleManager& module_manager, NetlistManager& netlist_manager,
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const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir, const std::string& submodule_dir_name,
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const FabricVerilogOption& options);
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2020-05-27 15:25:06 -05:00
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2022-10-06 19:08:50 -05:00
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void print_verilog_submodule_arch_decoders(
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const ModuleManager& module_manager, NetlistManager& netlist_manager,
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const DecoderLibrary& decoder_lib, const std::string& submodule_dir,
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const std::string& submodule_dir_name, const FabricVerilogOption& options);
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2020-05-27 15:25:06 -05:00
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2020-02-16 13:21:59 -06:00
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} /* end namespace openfpga */
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#endif
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