2020-11-10 15:32:24 -06:00
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/************************************************************************
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* Member functions for class TileAnnotation
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***********************************************************************/
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#include "tile_annotation.h"
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2022-10-06 19:08:50 -05:00
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#include "vtr_assert.h"
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2020-11-10 15:32:24 -06:00
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/* namespace openfpga begins */
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namespace openfpga {
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/************************************************************************
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* Constructors
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***********************************************************************/
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2022-10-06 19:08:50 -05:00
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TileAnnotation::TileAnnotation() { return; }
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2020-11-10 15:32:24 -06:00
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/************************************************************************
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* Public Accessors : aggregates
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***********************************************************************/
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TileAnnotation::global_port_range TileAnnotation::global_ports() const {
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return vtr::make_range(global_port_ids_.begin(), global_port_ids_.end());
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}
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/************************************************************************
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* Public Accessors
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***********************************************************************/
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2022-10-06 19:08:50 -05:00
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std::string TileAnnotation::global_port_name(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_names_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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std::vector<std::string> TileAnnotation::global_port_tile_names(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_tile_names_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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std::vector<BasicPort> TileAnnotation::global_port_tile_ports(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_tile_ports_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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std::vector<vtr::Point<size_t>> TileAnnotation::global_port_tile_coordinates(
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const TileGlobalPortId& global_port_id) const {
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2021-01-09 19:47:12 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_tile_coordinates_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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bool TileAnnotation::global_port_is_clock(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_is_clock_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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bool TileAnnotation::global_port_is_set(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_is_set_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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bool TileAnnotation::global_port_is_reset(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_is_reset_[global_port_id];
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}
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2022-10-06 19:08:50 -05:00
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size_t TileAnnotation::global_port_default_value(
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const TileGlobalPortId& global_port_id) const {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_default_values_[global_port_id];
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}
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2023-03-01 00:36:41 -06:00
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std::string TileAnnotation::global_port_clock_arch_tree_name(
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const TileGlobalPortId& global_port_id) const {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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return global_port_clock_arch_tree_names_[global_port_id];
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}
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2020-11-10 15:32:24 -06:00
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/************************************************************************
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* Public Mutators
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***********************************************************************/
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TileGlobalPortId TileAnnotation::create_global_port(
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const std::string& port_name) {
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2020-11-11 14:59:24 -06:00
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/* Ensure that the name is unique */
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std::map<std::string, TileGlobalPortId>::iterator it =
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global_port_name2ids_.find(port_name);
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2020-11-11 14:59:24 -06:00
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if (it != global_port_name2ids_.end()) {
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return TileGlobalPortId::INVALID();
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}
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2020-11-10 15:32:24 -06:00
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/* This is a legal name. we can create a new id */
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TileGlobalPortId port_id = TileGlobalPortId(global_port_ids_.size());
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global_port_ids_.push_back(port_id);
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global_port_names_.push_back(port_name);
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global_port_tile_names_.emplace_back();
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global_port_tile_ports_.emplace_back();
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global_port_tile_coordinates_.emplace_back();
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global_port_is_clock_.push_back(false);
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global_port_clock_arch_tree_names_.emplace_back();
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2020-11-10 15:32:24 -06:00
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global_port_is_set_.push_back(false);
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global_port_is_reset_.push_back(false);
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global_port_default_values_.push_back(0);
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2020-11-11 14:59:24 -06:00
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/* Register in the name-to-id map */
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global_port_name2ids_[port_name] = port_id;
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2020-11-10 15:32:24 -06:00
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return port_id;
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}
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2022-10-06 19:08:50 -05:00
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void TileAnnotation::add_global_port_tile_information(
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const TileGlobalPortId& global_port_id, const std::string& tile_name,
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const BasicPort& tile_port, const vtr::Point<size_t>& tile_coord) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_tile_names_[global_port_id].push_back(tile_name);
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global_port_tile_ports_[global_port_id].push_back(tile_port);
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global_port_tile_coordinates_[global_port_id].push_back(tile_coord);
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}
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2022-10-06 19:08:50 -05:00
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void TileAnnotation::set_global_port_is_clock(
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const TileGlobalPortId& global_port_id, const bool& is_clock) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_is_clock_[global_port_id] = is_clock;
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}
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2023-03-01 00:36:41 -06:00
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void TileAnnotation::set_global_port_clock_arch_tree_name(
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const TileGlobalPortId& global_port_id, const std::string& clock_tree_name) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_clock_arch_tree_names_[global_port_id] = clock_tree_name;
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}
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2022-10-06 19:08:50 -05:00
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void TileAnnotation::set_global_port_is_set(
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const TileGlobalPortId& global_port_id, const bool& is_set) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_is_set_[global_port_id] = is_set;
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}
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2022-10-06 19:08:50 -05:00
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void TileAnnotation::set_global_port_is_reset(
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const TileGlobalPortId& global_port_id, const bool& is_reset) {
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_is_reset_[global_port_id] = is_reset;
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}
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2022-10-06 19:08:50 -05:00
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void TileAnnotation::set_global_port_default_value(
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const TileGlobalPortId& global_port_id, const size_t& default_value) {
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2020-11-10 15:32:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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global_port_default_values_[global_port_id] = default_value;
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}
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/************************************************************************
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2022-10-06 19:08:50 -05:00
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* Internal invalidators/validators
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2020-11-10 15:32:24 -06:00
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***********************************************************************/
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/* Validators */
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2022-10-06 19:08:50 -05:00
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bool TileAnnotation::valid_global_port_id(
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const TileGlobalPortId& global_port_id) const {
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return (size_t(global_port_id) < global_port_ids_.size()) &&
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(global_port_id == global_port_ids_[global_port_id]);
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2020-11-10 15:32:24 -06:00
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}
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2022-10-06 19:08:50 -05:00
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bool TileAnnotation::valid_global_port_attributes(
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const TileGlobalPortId& global_port_id) const {
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2020-11-11 14:59:24 -06:00
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VTR_ASSERT(valid_global_port_id(global_port_id));
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int attribute_counter = 0;
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if (true == global_port_is_clock_[global_port_id]) {
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attribute_counter++;
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}
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if (true == global_port_is_reset_[global_port_id]) {
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attribute_counter++;
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}
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if (true == global_port_is_set_[global_port_id]) {
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attribute_counter++;
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}
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return ((0 == attribute_counter) || (1 == attribute_counter));
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}
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2022-10-06 19:08:50 -05:00
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} // namespace openfpga
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