2020-09-20 13:58:55 -05:00
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#ifndef VERILOG_SIMULATION_INFO_WRITER_H
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#define VERILOG_SIMULATION_INFO_WRITER_H
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2020-02-27 19:01:47 -06:00
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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2022-10-06 19:08:50 -05:00
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2020-07-01 14:07:39 -05:00
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#include "config_protocol.h"
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#include "io_location_map.h"
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2022-10-06 19:08:50 -05:00
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#include "module_manager.h"
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2021-06-25 11:10:16 -05:00
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#include "verilog_testbench_options.h"
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2022-10-06 19:08:50 -05:00
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#include "vpr_context.h"
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2020-02-27 19:01:47 -06:00
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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2022-10-06 19:08:50 -05:00
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void print_verilog_simulation_info(
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const std::string& ini_fname, const VerilogTestbenchOption& options,
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const std::string& circuit_name, const std::string& src_dir,
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const AtomContext& atom_ctx, const PlacementContext& place_ctx,
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const IoLocationMap& io_location_map, const ModuleManager& module_manager,
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const e_config_protocol_type& config_protocol_type,
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const size_t& num_program_clock_cycles, const int& num_operating_clock_cycles,
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const float& prog_clock_freq, const float& op_clock_freq);
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2020-02-27 19:01:47 -06:00
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} /* end namespace openfpga */
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#endif
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