OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/PC.v

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2020-07-22 13:33:52 -05:00
module PC(
output reg [3:0] pc_out,
input cp,
input clk,
input clr_
);
always @(posedge clk)
begin
if(~clr_) pc_out <= 0;
else if (cp) pc_out <= pc_out + 1;
end
endmodule