OpenFPGA/.travis/fpga_verilog_reg_test.sh

#!/bin/bash

set -e

start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd ${TRAVIS_BUILD_DIR}

source .github/workflows/fpga_verilog_reg_test.sh

end_section "OpenFPGA.TaskTun"
add missing files for Travis 2019-04-10 02:24:37 -05:00			`#!/bin/bash`

			`set -e`

Added travis fold for Python Task [ci skip] 2019-08-31 23:36:18 -05:00			`start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"`
remove simulation settings from openfpga arch XML update travis to split CI tests fix errors in travis configuration fixing travis errors in scripts keep fixing travis fix travis on build.sh bug fixing in travis CI bug fix in travis regression test run fixing bugs in the travis scripts bug fix in travis script: remove common.sh in regression test call keep bug fixing in travis 2020-06-11 13:05:12 -05:00			`cd ${TRAVIS_BUILD_DIR}`
add duplicate_grid_pin to travis integration 2019-12-30 15:06:20 -06:00
[Test] Now travis and github actions share the common regression test scripts 2020-11-24 16:58:09 -06:00			`source .github/workflows/fpga_verilog_reg_test.sh`
update travis script with example run on MCNC big20 2020-04-28 19:16:52 -05:00
Added travis fold for Python Task [ci skip] 2019-08-31 23:36:18 -05:00			`end_section "OpenFPGA.TaskTun"`