2018-07-26 12:28:21 -05:00
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#!/bin/sh
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# Example of how to run vpr
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# Pack, place, and route a heterogeneous FPGA
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# Packing uses the AAPack algorithm
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2018-12-08 12:33:14 -06:00
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./vpr ../../fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml Circuits/s298_prevpr.blif --full_stats --nodisp --activity_file Circuits/s298_prevpr.act --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_go --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_go --fpga_verilog_print_top_testbench
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2018-08-01 15:04:28 -05:00
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2018-07-26 12:28:21 -05:00
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