90 lines
4.4 KiB
C++
90 lines
4.4 KiB
C++
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/********************************************************************
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* This file includes most utilized functions that are used to
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* build module graphs
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********************************************************************/
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#include <vector>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "openfpga_naming.h"
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#include "build_module_graph_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Find input port of a buffer/inverter module
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********************************************************************/
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ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager,
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const ModuleId& module_id,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& model_id,
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const e_circuit_model_port_type& port_type) {
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/* We must have a valid module id */
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* Check the type of model */
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VTR_ASSERT(CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model_id));
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/* Add module nets to wire to the buffer module */
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/* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */
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std::vector<CircuitPortId> model_ports = circuit_lib.model_ports_by_type(model_id, port_type, true);
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VTR_ASSERT(1 == model_ports.size());
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/* Find the input and output module ports */
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ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0]));
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VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id));
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return module_port_id;
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}
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/********************************************************************
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* Add inverter/buffer module to a parent module
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* and complete the wiring to the input port of inverter/buffer
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* This function will return the wire created for the output port of inverter/buffer
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*
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* parent_module
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* +-----------------------------------------------------------------
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* |
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* | input_net output_net
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* | | |
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* | v +---------------+ v
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* | src_module_port --------->| child_module |-------->
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* | +---------------+
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*
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********************************************************************/
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ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager,
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const ModuleId& parent_module,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& model_id,
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const ModuleNetId& input_net) {
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/* We must have a valid module id */
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VTR_ASSERT(true == module_manager.valid_module_id(parent_module));
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std::string module_name = circuit_lib.model_name(model_id);
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ModuleId child_module = module_manager.find_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(child_module));
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ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_INPUT);
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ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_OUTPUT);
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/* Port size should be 1 ! */
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VTR_ASSERT(1 == module_manager.module_port(child_module, module_input_port_id).get_width());
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VTR_ASSERT(1 == module_manager.module_port(child_module, module_output_port_id).get_width());
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/* Instanciate a child module */
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size_t child_instance = module_manager.num_instance(parent_module, child_module);
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module_manager.add_child_module(parent_module, child_module);
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/* Use the net to connect to the input net of buffer */
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module_manager.add_module_net_sink(parent_module, input_net, child_module, child_instance, module_input_port_id, 0);
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/* Create a net to bridge the input inverter and LUT MUX */
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ModuleNetId output_net = module_manager.create_module_net(parent_module);
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module_manager.add_module_net_source(parent_module, output_net, child_module, child_instance, module_output_port_id, 0);
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return output_net;
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}
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} /* end namespace openfpga */
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